zephyr/arch/riscv/include/kernel_arch_func.h
Ederson de Souza be28de692c arch/riscv: Use arch_switch() for context swap
Enable `arch_switch()` as preparation for SMP support. This patch
doesn't try to keep support for old style context swap - only switch
based swap is supported, to keep things simple.

A fair amount of refactoring was done in this patch, specially regarding
the code that decides what to do about the ISR. In RISC-V, ECALL
instructions are used to signalize several events, such as user space
system calls, forced syscall, IRQ offload, return from syscall and
context switch. All those handled by the ISR - which also handles
interrupts. After refactor, this "dispatching" step is done at the
beginning of ISR (just after saving generic registers).

As with other platforms, the thread object itself is used as the thread
"switch handle" for the context swap.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-02-25 19:13:50 -05:00

71 lines
1.4 KiB
C

/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Private kernel definitions
*
* This file contains private kernel function/macro definitions and various
* other definitions for the RISCV processor architecture.
*/
#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_
#define ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_
#include <kernel_arch_data.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
#ifdef CONFIG_RISCV_PMP
void z_riscv_configure_static_pmp_regions(void);
#endif
static ALWAYS_INLINE void arch_kernel_init(void)
{
#ifdef CONFIG_RISCV_PMP
z_riscv_configure_static_pmp_regions();
#endif
}
void arch_switch(void *switch_to, void **switched_from);
FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
const z_arch_esf_t *esf);
static inline bool arch_is_in_isr(void)
{
#ifdef CONFIG_SMP
unsigned int key = arch_irq_lock();
bool ret = arch_curr_cpu()->nested != 0U;
arch_irq_unlock(key);
return ret;
#else
return _kernel.cpus[0].nested != 0U;
#endif
}
extern FUNC_NORETURN void z_riscv_userspace_enter(k_thread_entry_t user_entry,
void *p1, void *p2, void *p3,
uint32_t stack_end,
uint32_t stack_start);
#ifdef CONFIG_IRQ_OFFLOAD
int z_irq_do_offload(void);
#endif
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_ */