0369998e61
MIPS (Microprocessor without Interlocked Pipelined Stages) is a instruction set architecture (ISA) developed by MIPS Computer Systems, now MIPS Technologies. This commit provides MIPS architecture support to Zephyr. It is compatible with the MIPS32 Release 1 specification. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
54 lines
826 B
C
54 lines
826 B
C
/*
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* Copyright (c) 2020 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Full C support initialization
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*/
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#include <kernel_internal.h>
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#include <irq.h>
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static void interrupt_init(void)
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{
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extern char __isr_vec[];
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extern uint32_t mips_cp0_status_int_mask;
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unsigned long ebase;
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irq_lock();
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mips_cp0_status_int_mask = 0;
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ebase = 0x80000000;
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memcpy((void *)(ebase + 0x180), __isr_vec, 0x80);
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/*
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* Disable boot exception vector in BOOTROM,
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* use exception vector in RAM.
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*/
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write_c0_status(read_c0_status() & ~(ST0_BEV));
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}
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/**
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*
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* @brief Prepare to and run C code
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*
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* This routine prepares for the execution of and runs C code.
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*
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* @return N/A
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*/
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void _PrepC(void)
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{
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z_bss_zero();
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interrupt_init();
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z_cstart();
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CODE_UNREACHABLE;
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}
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