Rajavardhan Gundi 1fcd39b624 intel_s1000: define memctl_default.S and memerror-vector.S files ... Define memctl_default.S and memerror-vector.S files. A reference could be found in the Xtensa toolchain directories. These are required for using cavs21_LX6HiFi3_RF3_WB16 Xtensa CPU mainly in simulator. On boards which have ROM, these would have been already defined in the ROM. Hence, the contents of these files will be developed at a later time if required. Change-Id: Idf52397bb6880c136525e69f47e09defcba7f036 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>		2018-05-01 16:46:41 -04:00
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arc	arch: arc: add the support of STACK_SENTINEL	2018-04-17 10:50:12 -07:00
arm	arch/arm/soc/st_stm32: Fix typos in soc.h	2018-04-28 20:46:08 +05:30
common	drivers/interrupt_controller: Introduce multi-level interrupt support	2018-02-06 22:39:05 -05:00
nios2	cleanup: replace old jira numbers with GH issues	2018-03-26 13:13:04 -04:00
posix	kernel: Further unify _reschedule APIs	2018-04-24 03:57:20 +05:30
riscv32	arch: riscv32: fe310: Always-On domain adress definition	2018-04-05 08:08:08 -05:00
x86	x86: minnowboard: Enable the userspace mode	2018-04-25 14:46:00 -07:00
xtensa	intel_s1000: define memctl_default.S and memerror-vector.S files	2018-05-01 16:46:41 -04:00
CMakeLists.txt
Kconfig	kconfig: fix menuconfig	2018-04-30 09:22:48 -07:00