63c24d9d34
Update the NEORV32 SoC, peripheral drivers, and board to support NEORV32 v1.11.1. Notable changes include: - Optional RISC-V ISA Kconfigs are now selected on the board level. - Peripheral registers are now automatically reset in hardware, no need for software initialization code. - The NEORV32 GPIO controller now supports 32 pins, not 64. Interrupt support will be submitted in a separate PR. - Default board configuration has 64k RAM and is clocked at 18 MHz. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
37 lines
668 B
ArmAsm
37 lines
668 B
ArmAsm
/*
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* Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/toolchain.h>
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/* exports */
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GTEXT(__reset)
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/* imports */
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GTEXT(__initialize)
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SECTION_FUNC(reset, __reset)
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/* Disable interrupts */
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csrw mstatus, x0
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csrw mie, x0
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#ifdef CONFIG_USERSPACE
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/* Disable counter access outside M-mode */
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csrw mcounteren, x0
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#endif /* CONFIG_USERSPACE */
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/* Allow mcycle and minstret counters to increment */
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li x11, ~5
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csrw mcountinhibit, x11
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/* Zerorize counters */
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csrw mcycle, x0
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csrw mcycleh, x0
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csrw minstret, x0
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csrw minstreth, x0
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/* Jump to __initialize */
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call __initialize
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