ef4ec43e63
We want to simplify the maintenance burden and confusion of having more than one driver for the same kernel timer peripheral used on all Microchip MEC parts. The XEC version of the driver was converted register definitions in the driver. Register access is performed using Zephyr sys_read/write architecture specific inline routines. Driver DT YAML was updated to use phandle for the 32-bit basic timer used for ARCH_HAS_CUSTOM_BUSY_WAIT support, basic timer max value property, and GIRQ interrtup aggregator hardware information. SoC part Kconfigs, chip level/board level DTSI updated to use the unified driver. Signed-off-by: Scott Worley <scott.worley@microchip.com> |
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