William Tambe abeccfec28 xtensa: support for more than 32 interrupts ... This change add support for using more than 32 interrupts. Signed-off-by: William Tambe <williamt@cadence.com>		2025-06-27 08:59:56 -10:00
..
include	linker: Add ROM_SECTIONS location	2024-06-20 12:08:58 -04:00
_soc_inthandlers.h	xtensa: support for more than 32 interrupts	2025-06-27 08:59:56 -10:00
asm_ldo_management.h
asm_memory_management.h
CMakeLists.txt	intel_adsp: cavs: add gdb support	2025-06-23 12:32:44 -07:00
gdbstub.c	intel_adsp: cavs: add gdb support	2025-06-23 12:32:44 -07:00
irq.c
Kconfig	intel_adsp: cavs: add gdb support	2025-06-23 12:32:44 -07:00
Kconfig.defconfig.cavs_v25	soc: intel: adsp: tgl: ace: Set correct virtual memory size	2024-05-21 18:43:37 +02:00
Kconfig.defconfig.series	intel_adsp: cavs: add gdb support	2025-06-23 12:32:44 -07:00
Kconfig.soc
multiprocessing.c	kernel: remove kernel/internal/smp.h	2025-04-29 02:42:09 +02:00
power_down_cavs.S	soc: intel_adsp: cavs: fix power_down documentation	2024-04-10 15:55:21 +02:00
power.c	soc: intel_adsp: Fix typo in cavs/power.c comment	2025-06-06 08:43:15 +02:00
sram.c