3821e5db62
Properly configure the MAX32 SPIXF peripheral to use the SPIXF controller for transparent memory mapped reads, and enable the SPIXF main controller and use it for writes. Add support for testing XIP support to the nocopy sample, which requires flashing with OpenOCD with MAX32690 QSPI flash support. Signed-off-by: Pete Johanson <pete.johanson@analog.com>
82 lines
2.7 KiB
Plaintext
82 lines
2.7 KiB
Plaintext
/*
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* Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* Linker script for the Cortex-M platforms.
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*/
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#include <zephyr/linker/sections.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/linker/linker-tool.h>
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#if defined(CONFIG_NORDIC_QSPI_NOR) && defined(CONFIG_SOC_NRF5340_CPUAPP)
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/* On nRF5340, external flash is mapped in XIP region at 0x1000_0000. */
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#define EXTFLASH_NODE DT_INST(0, nordic_qspi_nor)
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#define EXTFLASH_ADDR 0x10000000
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#define EXTFLASH_SIZE DT_PROP_OR(EXTFLASH_NODE, size_in_bytes, \
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DT_PROP(EXTFLASH_NODE, size) / 8)
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#elif defined(CONFIG_FLASH_ADI_MAX32_SPIXF) && DT_NODE_EXISTS(DT_INST(0, adi_max32_spixf_nor))
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/* On MAX32 SPIXF, external flash is mapped in XIP region at 0x8000_0000. */
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#define EXTFLASH_NODE DT_INST(0, adi_max32_spixf_nor)
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#define EXTFLASH_ADDR DT_REG_ADDR(DT_INST(0, adi_max32_spixf_nor))
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#define EXTFLASH_SIZE DT_REG_SIZE(DT_INST(0, adi_max32_spixf_nor))
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#elif defined(CONFIG_STM32_MEMMAP) && DT_NODE_EXISTS(DT_INST(0, st_stm32_ospi_nor))
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/* On stm32 OSPI, external flash is mapped in XIP region at address given by the reg property. */
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#define EXTFLASH_NODE DT_INST(0, st_stm32_ospi_nor)
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#define EXTFLASH_ADDR DT_REG_ADDR_BY_IDX(DT_PARENT(EXTFLASH_NODE), 1)
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#define EXTFLASH_SIZE (DT_PROP(EXTFLASH_NODE, size) / 8)
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#elif defined(CONFIG_STM32_MEMMAP) && DT_NODE_EXISTS(DT_INST(0, st_stm32_qspi_nor))
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/* On stm32 QSPI, external flash is mapped in XIP region at address given by the reg property. */
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#define EXTFLASH_NODE DT_INST(0, st_stm32_qspi_nor)
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#define EXTFLASH_ADDR DT_REG_ADDR_BY_IDX(DT_PARENT(EXTFLASH_NODE), 1)
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#define EXTFLASH_SIZE (DT_PROP(EXTFLASH_NODE, size) / 8)
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#elif defined(CONFIG_STM32_MEMMAP) && DT_NODE_EXISTS(DT_INST(0, st_stm32_xspi_nor))
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/* On stm32 XSPI, external flash is mapped in XIP region at address given by the reg property. */
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#define EXTFLASH_NODE DT_INST(0, st_stm32_xspi_nor)
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#define EXTFLASH_ADDR DT_REG_ADDR_BY_IDX(DT_PARENT(EXTFLASH_NODE), 1)
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#define EXTFLASH_SIZE (DT_PROP(EXTFLASH_NODE, size) / 8)
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#elif defined(CONFIG_FLASH_MSPI_NOR) && defined(CONFIG_SOC_NRF54H20_CPUAPP)
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#define EXTFLASH_NODE DT_INST(0, jedec_mspi_nor)
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#define EXTFLASH_ADDR 0x60000000
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#define EXTFLASH_SIZE DT_PROP_OR(EXTFLASH_NODE, size_in_bytes, \
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DT_PROP(EXTFLASH_NODE, size) / 8)
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#else
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/*
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* Add another fake portion of FLASH to simulate a secondary or external FLASH
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* that we can do XIP from.
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*/
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#define EXTFLASH_ADDR 0x7000
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#define EXTFLASH_SIZE (CONFIG_FLASH_SIZE * 1K - EXTFLASH_ADDR)
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#endif
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MEMORY
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{
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EXTFLASH (rx) : ORIGIN = EXTFLASH_ADDR, LENGTH = EXTFLASH_SIZE
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}
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#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>
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