ef4ec43e63
We want to simplify the maintenance burden and confusion of having more than one driver for the same kernel timer peripheral used on all Microchip MEC parts. The XEC version of the driver was converted register definitions in the driver. Register access is performed using Zephyr sys_read/write architecture specific inline routines. Driver DT YAML was updated to use phandle for the 32-bit basic timer used for ARCH_HAS_CUSTOM_BUSY_WAIT support, basic timer max value property, and GIRQ interrtup aggregator hardware information. SoC part Kconfigs, chip level/board level DTSI updated to use the unified driver. Signed-off-by: Scott Worley <scott.worley@microchip.com>
36 lines
816 B
YAML
36 lines
816 B
YAML
# Copyright (c) 2025 Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: Microchip XEC basic timer properties
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compatible: "microchip,xec-basic-timer"
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include: ["base.yaml", "microchip,dmec-ecia-girq.yaml"]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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clock-frequency:
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type: int
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required: true
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const: 48000000
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description: Basic timer input clock is 48 MHz.
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max-value:
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type: int
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required: true
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description: |
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Counter maximum value. The SoC contains multiple instances
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of the basic timer. Some are 16-bit, others 32-bit.
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prescaler:
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type: int
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required: true
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description: |
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Basic timer implements a 16-bit clock prescale value.
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Count frequency is clock-frequency divided by (prescaler + 1).
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