2c1538d57e
Ensure consistent (and concise) short descriptions of all the st,*.yaml bindings Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
71 lines
1.5 KiB
YAML
71 lines
1.5 KiB
YAML
# Copyright (c) 2021, Linaro ltd
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32F4 Main PLL.
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Takes one of clk_hse or clk_hsi as input clock, with an
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input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
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in this acceptable range.
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Up to 2 output clocks could be supported and for each output clock, the
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frequency can be computed with the following formula:
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f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
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f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
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with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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The PLL output frequency must not exceed 80 MHz.
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compatible: "st,stm32f4-pll-clock"
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include: [clock-controller.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 0
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clocks:
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required: true
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div-m:
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type: int
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required: true
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description: |
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Division factor for the PLL input clock
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Valid range: 2 - 63
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mul-n:
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type: int
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required: true
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description: |
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Main PLL multiplication factor for VCO
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Valid range: 50 - 432
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div-p:
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type: int
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required: true
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description: |
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Main PLL division factor for PLLSAI2CLK
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enum:
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- 2
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- 4
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- 6
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- 8
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div-q:
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type: int
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description: |
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Main PLL (PLL) division factor for USB OTG FS, SDMMC and random number
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generator clocks.
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Valid range: 2 - 15
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div-r:
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type: int
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description: |
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Main PLL (PLL) division factor for I2S and DFSDM
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generator clocks.
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Valid range: 2 - 7
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