0a68d492e2
The new update of clock device tree make the pll p q r clock source cannot be choose by other node This fix add 1 new dts binding for pll out p q r out line Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
22 lines
386 B
YAML
22 lines
386 B
YAML
# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RA Clock Generation Circuit PLL Clock
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compatible: "renesas,ra-cgc-pll"
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include: [clock-controller.yaml, base.yaml]
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properties:
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clocks:
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required: true
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div:
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required: true
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type: int
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mul:
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required: true
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type: array
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"#clock-cells":
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const: 0
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