32229d0b6c
Block the SoC from re-entering sleep modes while the RX line is active, if the RX activity previously woke the device from the sleep states. This stops the device from continuously transitioning between the two modes and improves responsiveness. Signed-off-by: Jordan Yates <jordan@embeint.com>
111 lines
2.5 KiB
C
111 lines
2.5 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Driver for UART port on STM32 family processor.
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*
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*/
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#ifndef ZEPHYR_DRIVERS_SERIAL_UART_STM32_H_
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#define ZEPHYR_DRIVERS_SERIAL_UART_STM32_H_
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/reset.h>
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#include <zephyr/drivers/uart.h>
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#include <stm32_ll_usart.h>
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/* device config */
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struct uart_stm32_config {
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/* USART instance */
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USART_TypeDef *usart;
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/* Reset controller device configuration */
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const struct reset_dt_spec reset;
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/* clock subsystem driving this peripheral */
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const struct stm32_pclken *pclken;
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/* number of clock subsystems */
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size_t pclk_len;
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/* switch to enable single wire / half duplex feature */
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bool single_wire;
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/* enable tx/rx pin swap */
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bool tx_rx_swap;
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/* enable rx pin inversion */
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bool rx_invert;
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/* enable tx pin inversion */
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bool tx_invert;
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/* enable de signal */
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bool de_enable;
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/* de signal assertion time in 1/16 of a bit */
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uint8_t de_assert_time;
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/* de signal deassertion time in 1/16 of a bit */
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uint8_t de_deassert_time;
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/* enable de pin inversion */
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bool de_invert;
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/* enable fifo */
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bool fifo_enable;
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/* pin muxing */
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const struct pinctrl_dev_config *pcfg;
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#if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API) || \
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defined(CONFIG_PM)
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uart_irq_config_func_t irq_config_func;
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#endif
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#if defined(CONFIG_PM)
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/* Device defined as wake-up source */
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bool wakeup_source;
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uint32_t wakeup_line;
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#endif /* CONFIG_PM */
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};
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#ifdef CONFIG_UART_ASYNC_API
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struct uart_dma_stream {
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const struct device *dma_dev;
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uint32_t dma_channel;
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struct dma_config dma_cfg;
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uint8_t priority;
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bool src_addr_increment;
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bool dst_addr_increment;
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int fifo_threshold;
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struct dma_block_config blk_cfg;
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uint8_t *buffer;
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size_t buffer_length;
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size_t offset;
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volatile size_t counter;
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int32_t timeout;
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struct k_work_delayable timeout_work;
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bool enabled;
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};
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#endif
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/* driver data */
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struct uart_stm32_data {
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/* clock device */
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const struct device *clock;
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/* uart config */
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struct uart_config *uart_cfg;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t user_cb;
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void *user_data;
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#endif
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#ifdef CONFIG_UART_ASYNC_API
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const struct device *uart_dev;
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uart_callback_t async_cb;
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void *async_user_data;
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struct uart_dma_stream dma_rx;
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struct uart_dma_stream dma_tx;
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uint8_t *rx_next_buffer;
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size_t rx_next_buffer_len;
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#endif
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#ifdef CONFIG_PM
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bool tx_poll_stream_on;
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bool tx_int_stream_on;
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bool pm_policy_state_on;
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bool rx_woken;
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#endif
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};
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#endif /* ZEPHYR_DRIVERS_SERIAL_UART_STM32_H_ */
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