fa199b6f6c
Two DMA channels are assigned to TX and RX respectively: - A TX DMA request is asserted when there is space in the FIFO. - A RX DMA request is asserted when data is in the FIFO. When DMA is enabled for a peripheral, the DMA transfer completion is signaled on the peripheral's interrupt only (here UART's interrupt). It is not signaled on the DMA dedicated interrupt. Also, when DMA is enabled for a peripheral, the DMA controller stops the normal transfer interrupts for this peripheral from reaching the NVIC (the interrupts are still reported in the interrupt registers of the peripheral). Thus, when a large amount of data is transferred using DMA, instead of receiving multiple interrupts from the peripheral as data flows, the NVIC receives only one interrupt when the transfer completes (unmasked peripheral error interrupts continue to be sent to the NVIC). Signed-off-by: Julien Panis <jpanis@baylibre.com>
909 lines
25 KiB
C
909 lines
25 KiB
C
/*
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* Copyright (c) 2024 Texas Instruments Incorporated
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* Copyright (c) 2024 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_cc23x0_uart
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#include <zephyr/device.h>
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#include <zephyr/drivers/dma.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/irq.h>
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#include <errno.h>
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#include <driverlib/uart.h>
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#include <driverlib/clkctl.h>
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#include <inc/hw_memmap.h>
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#ifdef CONFIG_UART_CC23X0_DMA_DRIVEN
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#define UART_CC23_REG_GET(base, offset) ((base) + (offset))
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/*
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* For each DMA channel, burst transfer and single transfer request signals
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* are not mutually exclusive, and both can be asserted at the same time.
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* For example, when there is more data than the watermark level in the
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* TX (or RX) FIFO, the burst transfer request and the single transfer
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* requests are asserted.
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* When a burst request is detected, the DMA controller transfers the number
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* of items that is the lesser of the arbitration size or the number of items
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* remaining in the transfer. Therefore, the arbitration size must be the same
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* as the number of data items that the peripheral can accommodate when making
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* a burst request. Since UART, which uses a mix of single or burst requests,
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* can generate a burst request based on the FIFO trigger level (1/2 full),
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* the burst length is set to half the FIFO size.
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*/
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#define UART_CC23_BURST_LEN 4
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#endif
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struct uart_cc23x0_config {
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uint32_t reg;
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uint32_t sys_clk_freq;
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const struct pinctrl_dev_config *pcfg;
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#ifdef CONFIG_UART_CC23X0_DMA_DRIVEN
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const struct device *dma_dev;
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uint8_t dma_channel_tx;
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uint8_t dma_trigsrc_tx;
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uint8_t dma_channel_rx;
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uint8_t dma_trigsrc_rx;
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#endif
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};
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struct uart_cc23x0_data {
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struct uart_config uart_config;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t callback;
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void *user_data;
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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#ifdef CONFIG_UART_CC23X0_DMA_DRIVEN
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const struct device *dev;
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uart_callback_t async_callback;
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void *async_user_data;
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struct k_work_delayable tx_timeout_work;
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const uint8_t *tx_buf;
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size_t tx_len;
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uint8_t *rx_buf;
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size_t rx_len;
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size_t rx_processed_len;
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uint8_t *rx_next_buf;
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size_t rx_next_len;
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#endif /* CONFIG_UART_CC23X0_DMA_DRIVEN */
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};
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static int uart_cc23x0_poll_in(const struct device *dev, unsigned char *c)
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{
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const struct uart_cc23x0_config *config = dev->config;
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if (!UARTCharAvailable(config->reg)) {
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return -1;
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}
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*c = UARTGetCharNonBlocking(config->reg);
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return 0;
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}
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static void uart_cc23x0_poll_out(const struct device *dev, unsigned char c)
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{
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const struct uart_cc23x0_config *config = dev->config;
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UARTPutChar(config->reg, c);
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}
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static int uart_cc23x0_err_check(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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uint32_t flags = UARTGetRxError(config->reg);
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int error = 0;
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error |= (flags & UART_RXERROR_FRAMING) ? UART_ERROR_FRAMING : 0;
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error |= (flags & UART_RXERROR_PARITY) ? UART_ERROR_PARITY : 0;
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error |= (flags & UART_RXERROR_BREAK) ? UART_BREAK : 0;
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error |= (flags & UART_RXERROR_OVERRUN) ? UART_ERROR_OVERRUN : 0;
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UARTClearRxError(config->reg);
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return error;
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}
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static int uart_cc23x0_configure(const struct device *dev, const struct uart_config *cfg)
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{
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const struct uart_cc23x0_config *config = dev->config;
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struct uart_cc23x0_data *data = dev->data;
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uint32_t line_ctrl = 0;
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bool flow_ctrl;
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switch (cfg->parity) {
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case UART_CFG_PARITY_NONE:
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line_ctrl |= UART_CONFIG_PAR_NONE;
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break;
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case UART_CFG_PARITY_ODD:
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line_ctrl |= UART_CONFIG_PAR_ODD;
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break;
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case UART_CFG_PARITY_EVEN:
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line_ctrl |= UART_CONFIG_PAR_EVEN;
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break;
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case UART_CFG_PARITY_MARK:
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line_ctrl |= UART_CONFIG_PAR_ONE;
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break;
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case UART_CFG_PARITY_SPACE:
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line_ctrl |= UART_CONFIG_PAR_ZERO;
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break;
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default:
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return -EINVAL;
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}
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switch (cfg->stop_bits) {
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case UART_CFG_STOP_BITS_1:
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line_ctrl |= UART_CONFIG_STOP_ONE;
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break;
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case UART_CFG_STOP_BITS_2:
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line_ctrl |= UART_CONFIG_STOP_TWO;
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break;
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case UART_CFG_STOP_BITS_0_5:
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case UART_CFG_STOP_BITS_1_5:
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return -ENOTSUP;
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default:
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return -EINVAL;
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}
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switch (cfg->data_bits) {
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case UART_CFG_DATA_BITS_5:
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line_ctrl |= UART_CONFIG_WLEN_5;
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break;
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case UART_CFG_DATA_BITS_6:
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line_ctrl |= UART_CONFIG_WLEN_6;
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break;
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case UART_CFG_DATA_BITS_7:
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line_ctrl |= UART_CONFIG_WLEN_7;
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break;
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case UART_CFG_DATA_BITS_8:
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line_ctrl |= UART_CONFIG_WLEN_8;
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break;
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default:
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return -EINVAL;
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}
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switch (cfg->flow_ctrl) {
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case UART_CFG_FLOW_CTRL_NONE:
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flow_ctrl = false;
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break;
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case UART_CFG_FLOW_CTRL_RTS_CTS:
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flow_ctrl = true;
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break;
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case UART_CFG_FLOW_CTRL_DTR_DSR:
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return -ENOTSUP;
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default:
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return -EINVAL;
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}
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/* Disables UART before setting control registers */
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UARTConfigSetExpClk(config->reg, config->sys_clk_freq, cfg->baudrate, line_ctrl);
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if (flow_ctrl) {
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UARTEnableCTS(config->reg);
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UARTEnableRTS(config->reg);
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} else {
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UARTDisableCTS(config->reg);
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UARTDisableRTS(config->reg);
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}
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/* Re-enable UART */
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UARTEnable(config->reg);
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/* Make use of the FIFO to reduce chances of data being lost */
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UARTEnableFifo(config->reg);
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data->uart_config = *cfg;
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return 0;
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}
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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static int uart_cc23x0_config_get(const struct device *dev, struct uart_config *cfg)
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{
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const struct uart_cc23x0_data *data = dev->data;
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*cfg = data->uart_config;
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return 0;
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}
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_cc23x0_fifo_fill(const struct device *dev, const uint8_t *buf, int len)
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{
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const struct uart_cc23x0_config *config = dev->config;
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int n = 0;
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while (n < len) {
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if (!UARTSpaceAvailable(config->reg)) {
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break;
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}
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UARTPutCharNonBlocking(config->reg, buf[n]);
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n++;
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}
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return n;
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}
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static int uart_cc23x0_fifo_read(const struct device *dev, uint8_t *buf, const int len)
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{
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const struct uart_cc23x0_config *config = dev->config;
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int c, n;
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n = 0;
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while (n < len) {
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if (!UARTCharAvailable(config->reg)) {
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break;
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}
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c = UARTGetCharNonBlocking(config->reg);
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buf[n++] = c;
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}
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return n;
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}
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static void uart_cc23x0_irq_tx_enable(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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UARTEnableInt(config->reg, UART_INT_TX);
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}
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static void uart_cc23x0_irq_tx_disable(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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UARTDisableInt(config->reg, UART_INT_TX);
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}
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static int uart_cc23x0_irq_tx_ready(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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return UARTSpaceAvailable(config->reg) ? 1 : 0;
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}
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static void uart_cc23x0_irq_rx_enable(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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/* Trigger the ISR on both RX and Receive Timeout. This is to allow
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* the use of the hardware FIFOs for more efficient operation
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*/
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UARTEnableInt(config->reg, UART_INT_RX | UART_INT_RT);
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}
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static void uart_cc23x0_irq_rx_disable(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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UARTDisableInt(config->reg, UART_INT_RX | UART_INT_RT);
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}
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static int uart_cc23x0_irq_tx_complete(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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return UARTBusy(config->reg) ? 0 : 1;
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}
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static int uart_cc23x0_irq_rx_ready(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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return UARTCharAvailable(config->reg) ? 1 : 0;
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}
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static void uart_cc23x0_irq_err_enable(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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return UARTEnableInt(config->reg, UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE);
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}
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static void uart_cc23x0_irq_err_disable(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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return UARTDisableInt(config->reg, UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE);
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}
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static int uart_cc23x0_irq_is_pending(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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/* Read masked interrupt status */
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uint32_t status = UARTIntStatus(config->reg, true);
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return status ? 1 : 0;
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}
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static int uart_cc23x0_irq_update(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 1;
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}
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static void uart_cc23x0_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
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void *user_data)
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{
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struct uart_cc23x0_data *data = dev->data;
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data->callback = cb;
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data->user_data = user_data;
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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#if CONFIG_UART_CC23X0_DMA_DRIVEN
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static int uart_cc23x0_async_callback_set(const struct device *dev, uart_callback_t callback,
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void *user_data)
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{
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struct uart_cc23x0_data *data = dev->data;
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#if defined(CONFIG_UART_EXCLUSIVE_API_CALLBACKS)
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data->async_callback = NULL;
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data->async_user_data = NULL;
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#else
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data->async_callback = callback;
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data->async_user_data = user_data;
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#endif
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return 0;
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}
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static int uart_cc23x0_async_tx(const struct device *dev, const uint8_t *buf, size_t len,
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int32_t timeout)
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{
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const struct uart_cc23x0_config *config = dev->config;
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struct uart_cc23x0_data *data = dev->data;
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unsigned int key;
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int ret;
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struct dma_block_config block_cfg_tx = {
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.source_address = (uint32_t)buf,
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.dest_address = UART_CC23_REG_GET(config->reg, UART_O_DR),
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.source_addr_adj = DMA_ADDR_ADJ_INCREMENT,
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.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE,
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.block_size = len,
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};
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struct dma_config dma_cfg_tx = {
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.dma_slot = config->dma_trigsrc_tx,
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.channel_direction = MEMORY_TO_PERIPHERAL,
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.block_count = 1,
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.head_block = &block_cfg_tx,
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.source_data_size = 1,
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.dest_data_size = 1,
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.source_burst_length = UART_CC23_BURST_LEN,
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.dma_callback = NULL,
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.user_data = NULL,
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};
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key = irq_lock();
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if (data->tx_len) {
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irq_unlock(key);
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return -EBUSY;
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}
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data->tx_buf = buf;
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data->tx_len = len;
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irq_unlock(key);
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ret = dma_config(config->dma_dev, config->dma_channel_tx, &dma_cfg_tx);
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if (ret) {
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return ret;
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}
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/* Disable DMA trigger */
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UARTDisableDMA(config->reg, UART_DMA_TX);
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/* Schedule timeout work */
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if (timeout != SYS_FOREVER_US) {
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k_work_reschedule(&data->tx_timeout_work, K_USEC(timeout));
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}
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/* Start DMA channel */
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ret = dma_start(config->dma_dev, config->dma_channel_tx);
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if (ret) {
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return ret;
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}
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/* Enable DMA trigger to start the transfer */
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UARTEnableDMA(config->reg, UART_DMA_TX);
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return 0;
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}
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static int uart_cc23x0_tx_halt(struct uart_cc23x0_data *data)
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{
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const struct uart_cc23x0_config *config = data->dev->config;
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struct dma_status status;
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struct uart_event evt;
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size_t total_len;
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unsigned int key;
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key = irq_lock();
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total_len = data->tx_len;
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evt.type = UART_TX_ABORTED;
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evt.data.tx.buf = data->tx_buf;
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evt.data.tx.len = 0;
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data->tx_buf = NULL;
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data->tx_len = 0;
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dma_stop(config->dma_dev, config->dma_channel_tx);
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irq_unlock(key);
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if (dma_get_status(config->dma_dev, config->dma_channel_tx, &status) == 0) {
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evt.data.tx.len = total_len - status.pending_length;
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}
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if (total_len) {
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if (data->async_callback) {
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data->async_callback(data->dev, &evt, data->async_user_data);
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}
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} else {
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return -EINVAL;
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}
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return 0;
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}
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static void uart_cc23x0_async_tx_timeout(struct k_work *work)
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{
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struct k_work_delayable *dwork = k_work_delayable_from_work(work);
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struct uart_cc23x0_data *data = CONTAINER_OF(dwork, struct uart_cc23x0_data,
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tx_timeout_work);
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uart_cc23x0_tx_halt(data);
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}
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static int uart_cc23x0_async_tx_abort(const struct device *dev)
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{
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struct uart_cc23x0_data *data = dev->data;
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k_work_cancel_delayable(&data->tx_timeout_work);
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return uart_cc23x0_tx_halt(data);
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}
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static int uart_cc23x0_async_rx_enable(const struct device *dev, uint8_t *buf, size_t len,
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int32_t timeout)
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{
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const struct uart_cc23x0_config *config = dev->config;
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struct uart_cc23x0_data *data = dev->data;
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struct uart_event evt;
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unsigned int key;
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int ret;
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struct dma_block_config block_cfg_rx = {
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.source_address = UART_CC23_REG_GET(config->reg, UART_O_DR),
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.dest_address = (uint32_t)buf,
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.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE,
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.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT,
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.block_size = len,
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};
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struct dma_config dma_cfg_rx = {
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.dma_slot = config->dma_trigsrc_rx,
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.channel_direction = PERIPHERAL_TO_MEMORY,
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.block_count = 1,
|
|
.head_block = &block_cfg_rx,
|
|
.source_data_size = 1,
|
|
.dest_data_size = 1,
|
|
.source_burst_length = UART_CC23_BURST_LEN,
|
|
.dma_callback = NULL,
|
|
.user_data = NULL,
|
|
};
|
|
|
|
if (timeout != SYS_FOREVER_US) {
|
|
return -ENOTSUP;
|
|
}
|
|
|
|
key = irq_lock();
|
|
|
|
if (data->rx_len) {
|
|
ret = -EBUSY;
|
|
goto unlock;
|
|
}
|
|
|
|
ret = dma_config(config->dma_dev, config->dma_channel_rx, &dma_cfg_rx);
|
|
if (ret) {
|
|
goto unlock;
|
|
}
|
|
|
|
/* Disable DMA trigger */
|
|
UARTDisableDMA(config->reg, UART_DMA_RX);
|
|
|
|
/* Start DMA channel */
|
|
ret = dma_start(config->dma_dev, config->dma_channel_rx);
|
|
if (ret) {
|
|
goto unlock;
|
|
}
|
|
|
|
/* Enable DMA trigger to start the transfer */
|
|
UARTEnableDMA(config->reg, UART_DMA_RX);
|
|
|
|
data->rx_buf = buf;
|
|
data->rx_len = len;
|
|
data->rx_processed_len = 0;
|
|
|
|
/* Request next buffer */
|
|
if (data->async_callback) {
|
|
evt.type = UART_RX_BUF_REQUEST;
|
|
|
|
data->async_callback(dev, &evt, data->async_user_data);
|
|
}
|
|
|
|
unlock:
|
|
irq_unlock(key);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int uart_cc23x0_async_rx_buf_rsp(const struct device *dev, uint8_t *buf, size_t len)
|
|
{
|
|
struct uart_cc23x0_data *data = dev->data;
|
|
unsigned int key;
|
|
int ret = 0;
|
|
|
|
key = irq_lock();
|
|
|
|
if (data->rx_len == 0) {
|
|
ret = -EACCES;
|
|
goto unlock;
|
|
}
|
|
|
|
if (data->rx_next_len) {
|
|
ret = -EBUSY;
|
|
goto unlock;
|
|
}
|
|
|
|
data->rx_next_buf = buf;
|
|
data->rx_next_len = len;
|
|
|
|
unlock:
|
|
irq_unlock(key);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void uart_cc23x0_notify_rx_processed(struct uart_cc23x0_data *data,
|
|
size_t processed)
|
|
{
|
|
struct uart_event evt;
|
|
|
|
if (!data->async_callback || data->rx_processed_len == processed) {
|
|
return;
|
|
}
|
|
|
|
evt.type = UART_RX_RDY;
|
|
evt.data.rx.buf = data->rx_buf;
|
|
evt.data.rx.offset = data->rx_processed_len;
|
|
evt.data.rx.len = processed - data->rx_processed_len;
|
|
|
|
data->rx_processed_len = processed;
|
|
|
|
data->async_callback(data->dev, &evt, data->async_user_data);
|
|
}
|
|
|
|
static int uart_cc23x0_async_rx_disable(const struct device *dev)
|
|
{
|
|
const struct uart_cc23x0_config *config = dev->config;
|
|
struct uart_cc23x0_data *data = dev->data;
|
|
struct dma_status status;
|
|
struct uart_event evt;
|
|
size_t rx_processed;
|
|
unsigned int key;
|
|
int ret = 0;
|
|
|
|
key = irq_lock();
|
|
|
|
if (data->rx_len == 0) {
|
|
ret = -EINVAL;
|
|
goto unlock;
|
|
}
|
|
|
|
dma_stop(config->dma_dev, config->dma_channel_rx);
|
|
|
|
if (dma_get_status(config->dma_dev, config->dma_channel_rx, &status) == 0 &&
|
|
status.pending_length) {
|
|
rx_processed = data->rx_len - status.pending_length;
|
|
|
|
uart_cc23x0_notify_rx_processed(data, rx_processed);
|
|
}
|
|
|
|
if (data->async_callback) {
|
|
evt.type = UART_RX_BUF_RELEASED;
|
|
evt.data.rx_buf.buf = data->rx_buf;
|
|
|
|
data->async_callback(dev, &evt, data->async_user_data);
|
|
}
|
|
|
|
data->rx_buf = NULL;
|
|
data->rx_len = 0;
|
|
|
|
if (data->rx_next_len) {
|
|
if (data->async_callback) {
|
|
evt.type = UART_RX_BUF_RELEASED;
|
|
evt.data.rx_buf.buf = data->rx_next_buf;
|
|
|
|
data->async_callback(dev, &evt, data->async_user_data);
|
|
}
|
|
|
|
data->rx_next_buf = NULL;
|
|
data->rx_next_len = 0;
|
|
}
|
|
|
|
if (data->async_callback) {
|
|
evt.type = UART_RX_DISABLED;
|
|
|
|
data->async_callback(dev, &evt, data->async_user_data);
|
|
}
|
|
|
|
unlock:
|
|
irq_unlock(key);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#endif /* CONFIG_UART_CC23X0_DMA_DRIVEN */
|
|
|
|
#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_CC23X0_DMA_DRIVEN
|
|
|
|
static void uart_cc23x0_isr(const struct device *dev)
|
|
{
|
|
struct uart_cc23x0_data *data = dev->data;
|
|
#if CONFIG_UART_CC23X0_DMA_DRIVEN
|
|
const struct uart_cc23x0_config *config = dev->config;
|
|
struct uart_event evt;
|
|
unsigned int key;
|
|
uint32_t int_status = UARTIntStatus(config->reg, true);
|
|
#endif
|
|
|
|
#if CONFIG_UART_INTERRUPT_DRIVEN
|
|
if (data->callback) {
|
|
data->callback(dev, data->user_data);
|
|
}
|
|
#endif
|
|
|
|
#if CONFIG_UART_CC23X0_DMA_DRIVEN
|
|
/*
|
|
* When a peripheral channel is used (which is the case here for UART),
|
|
* the DMA transfer completion is signaled on the peripheral's interrupt only.
|
|
* It is not signaled on the DMA dedicated interrupt.
|
|
*/
|
|
if (int_status & UART_INT_TXDMADONE) {
|
|
k_work_cancel_delayable(&data->tx_timeout_work);
|
|
|
|
key = irq_lock();
|
|
|
|
if (data->tx_len && data->async_callback) {
|
|
evt.type = UART_TX_DONE;
|
|
evt.data.tx.buf = data->tx_buf;
|
|
evt.data.tx.len = data->tx_len;
|
|
|
|
data->async_callback(dev, &evt, data->async_user_data);
|
|
}
|
|
|
|
data->tx_buf = NULL;
|
|
data->tx_len = 0;
|
|
|
|
irq_unlock(key);
|
|
|
|
UARTClearInt(config->reg, UART_INT_TXDMADONE);
|
|
}
|
|
|
|
if (int_status & UART_INT_RXDMADONE) {
|
|
key = irq_lock();
|
|
|
|
uart_cc23x0_notify_rx_processed(data, data->rx_len);
|
|
|
|
if (data->async_callback) {
|
|
evt.type = UART_RX_BUF_RELEASED;
|
|
evt.data.rx.buf = data->rx_buf;
|
|
|
|
data->async_callback(dev, &evt, data->async_user_data);
|
|
}
|
|
|
|
if (data->rx_next_len == 0) {
|
|
/* If no next buffer, end the transfer */
|
|
data->rx_buf = NULL;
|
|
data->rx_len = 0;
|
|
|
|
if (data->async_callback) {
|
|
evt.type = UART_RX_DISABLED;
|
|
|
|
data->async_callback(dev, &evt, data->async_user_data);
|
|
}
|
|
} else {
|
|
/* Otherwise, load next buffer and start the transfer */
|
|
data->rx_buf = data->rx_next_buf;
|
|
data->rx_len = data->rx_next_len;
|
|
data->rx_next_buf = NULL;
|
|
data->rx_next_len = 0;
|
|
data->rx_processed_len = 0;
|
|
|
|
dma_reload(config->dma_dev, config->dma_channel_rx,
|
|
(uint32_t)UART_CC23_REG_GET(config->reg, UART_O_DR),
|
|
(uint32_t)data->rx_buf, data->rx_len);
|
|
|
|
dma_start(config->dma_dev, config->dma_channel_rx);
|
|
|
|
/* Request a new buffer */
|
|
if (data->async_callback) {
|
|
evt.type = UART_RX_BUF_REQUEST;
|
|
|
|
data->async_callback(dev, &evt, data->async_user_data);
|
|
}
|
|
}
|
|
|
|
irq_unlock(key);
|
|
|
|
UARTClearInt(config->reg, UART_INT_RXDMADONE);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_CC23X0_DMA_DRIVEN */
|
|
|
|
static DEVICE_API(uart, uart_cc23x0_driver_api) = {
|
|
.poll_in = uart_cc23x0_poll_in,
|
|
.poll_out = uart_cc23x0_poll_out,
|
|
.err_check = uart_cc23x0_err_check,
|
|
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
|
|
.configure = uart_cc23x0_configure,
|
|
.config_get = uart_cc23x0_config_get,
|
|
#endif
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
.fifo_fill = uart_cc23x0_fifo_fill,
|
|
.fifo_read = uart_cc23x0_fifo_read,
|
|
.irq_tx_enable = uart_cc23x0_irq_tx_enable,
|
|
.irq_tx_disable = uart_cc23x0_irq_tx_disable,
|
|
.irq_tx_ready = uart_cc23x0_irq_tx_ready,
|
|
.irq_rx_enable = uart_cc23x0_irq_rx_enable,
|
|
.irq_rx_disable = uart_cc23x0_irq_rx_disable,
|
|
.irq_tx_complete = uart_cc23x0_irq_tx_complete,
|
|
.irq_rx_ready = uart_cc23x0_irq_rx_ready,
|
|
.irq_err_enable = uart_cc23x0_irq_err_enable,
|
|
.irq_err_disable = uart_cc23x0_irq_err_disable,
|
|
.irq_is_pending = uart_cc23x0_irq_is_pending,
|
|
.irq_update = uart_cc23x0_irq_update,
|
|
.irq_callback_set = uart_cc23x0_irq_callback_set,
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
|
#if CONFIG_UART_CC23X0_DMA_DRIVEN
|
|
.callback_set = uart_cc23x0_async_callback_set,
|
|
.tx = uart_cc23x0_async_tx,
|
|
.tx_abort = uart_cc23x0_async_tx_abort,
|
|
.rx_enable = uart_cc23x0_async_rx_enable,
|
|
.rx_buf_rsp = uart_cc23x0_async_rx_buf_rsp,
|
|
.rx_disable = uart_cc23x0_async_rx_disable,
|
|
#endif /* CONFIG_UART_CC23X0_DMA_DRIVEN */
|
|
};
|
|
|
|
#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_CC23X0_DMA_DRIVEN
|
|
#define UART_CC23X0_IRQ_CFG(n) \
|
|
const struct uart_cc23x0_config *config = dev->config; \
|
|
\
|
|
do { \
|
|
UARTClearInt(config->reg, UART_INT_RX); \
|
|
UARTClearInt(config->reg, UART_INT_RT); \
|
|
\
|
|
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), uart_cc23x0_isr, \
|
|
DEVICE_DT_INST_GET(n), 0); \
|
|
irq_enable(DT_INST_IRQN(n)); \
|
|
} while (false)
|
|
|
|
#else
|
|
#define UART_CC23X0_IRQ_CFG(n)
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_CC23X0_DMA_DRIVEN */
|
|
|
|
#if CONFIG_UART_INTERRUPT_DRIVEN
|
|
#define UART_CC23X0_INT_FIELDS .callback = NULL, .user_data = NULL,
|
|
#else
|
|
#define UART_CC23X0_INT_FIELDS
|
|
#endif
|
|
|
|
#ifdef CONFIG_UART_CC23X0_DMA_DRIVEN
|
|
#define UART_CC23X0_DMA_INIT(n) \
|
|
.dma_dev = DEVICE_DT_GET(TI_CC23X0_DT_INST_DMA_CTLR(n, tx)), \
|
|
.dma_channel_tx = TI_CC23X0_DT_INST_DMA_CHANNEL(n, tx), \
|
|
.dma_trigsrc_tx = TI_CC23X0_DT_INST_DMA_TRIGSRC(n, tx), \
|
|
.dma_channel_rx = TI_CC23X0_DT_INST_DMA_CHANNEL(n, rx), \
|
|
.dma_trigsrc_rx = TI_CC23X0_DT_INST_DMA_TRIGSRC(n, rx),
|
|
#else
|
|
#define UART_CC23X0_DMA_INIT(n)
|
|
#endif
|
|
|
|
static int uart_cc23x0_init_common(const struct device *dev)
|
|
{
|
|
const struct uart_cc23x0_config *config = dev->config;
|
|
struct uart_cc23x0_data *data = dev->data;
|
|
int ret;
|
|
|
|
CLKCTLEnable(CLKCTL_BASE, CLKCTL_UART0);
|
|
|
|
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
|
|
if (ret < 0) {
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_UART_CC23X0_DMA_DRIVEN
|
|
if (!device_is_ready(config->dma_dev)) {
|
|
return -ENODEV;
|
|
}
|
|
|
|
UARTEnableInt(config->reg, UART_INT_TXDMADONE | UART_INT_RXDMADONE);
|
|
|
|
k_work_init_delayable(&data->tx_timeout_work, uart_cc23x0_async_tx_timeout);
|
|
|
|
data->dev = dev;
|
|
#endif
|
|
|
|
/* Configure and enable UART */
|
|
return uart_cc23x0_configure(dev, &data->uart_config);
|
|
}
|
|
|
|
#define UART_CC23X0_DEVICE_DEFINE(n) \
|
|
\
|
|
DEVICE_DT_INST_DEFINE(n, uart_cc23x0_init_##n, NULL, &uart_cc23x0_data_##n, \
|
|
&uart_cc23x0_config_##n, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
|
|
&uart_cc23x0_driver_api)
|
|
|
|
#define UART_CC23X0_INIT_FUNC(n) \
|
|
static int uart_cc23x0_init_##n(const struct device *dev) \
|
|
{ \
|
|
int ret; \
|
|
\
|
|
ret = uart_cc23x0_init_common(dev); \
|
|
if (ret < 0) { \
|
|
return ret; \
|
|
} \
|
|
\
|
|
/* Enable interrupts */ \
|
|
UART_CC23X0_IRQ_CFG(n); \
|
|
\
|
|
return ret; \
|
|
}
|
|
|
|
#define UART_CC23X0_INIT(n) \
|
|
PINCTRL_DT_INST_DEFINE(n); \
|
|
UART_CC23X0_INIT_FUNC(n); \
|
|
\
|
|
static struct uart_cc23x0_config uart_cc23x0_config_##n = { \
|
|
.reg = DT_INST_REG_ADDR(n), \
|
|
.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \
|
|
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
|
|
UART_CC23X0_DMA_INIT(n) \
|
|
}; \
|
|
\
|
|
static struct uart_cc23x0_data uart_cc23x0_data_##n = { \
|
|
.uart_config = \
|
|
{ \
|
|
.baudrate = DT_INST_PROP(n, current_speed), \
|
|
.parity = DT_INST_ENUM_IDX(n, parity), \
|
|
.stop_bits = DT_INST_ENUM_IDX(n, stop_bits), \
|
|
.data_bits = DT_INST_ENUM_IDX(n, data_bits), \
|
|
.flow_ctrl = DT_INST_PROP(n, hw_flow_control), \
|
|
}, \
|
|
UART_CC23X0_INT_FIELDS \
|
|
}; \
|
|
UART_CC23X0_DEVICE_DEFINE(n);
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(UART_CC23X0_INIT)
|