f47bfebd28
Use the device API macro to place the driver API instance into an iterable section. Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
642 lines
16 KiB
C
642 lines
16 KiB
C
/*
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* Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT atmel_sam0_rtc
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/** @file
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* @brief RTC driver for Atmel SAM0 MCU family.
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*/
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#include <stdlib.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/rtc.h>
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#include "rtc_utils.h"
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(rtc_sam0, CONFIG_RTC_LOG_LEVEL);
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/* clang-format off */
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#define RTC_SAM0_TIME_MASK \
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(RTC_ALARM_TIME_MASK_SECOND \
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| RTC_ALARM_TIME_MASK_MINUTE \
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| RTC_ALARM_TIME_MASK_HOUR \
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| RTC_ALARM_TIME_MASK_MONTHDAY \
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| RTC_ALARM_TIME_MASK_MONTH \
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| RTC_ALARM_TIME_MASK_YEAR \
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)
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#define RTC_SAM0_CALIBRATE_PPB_MAX (127)
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#define RTC_SAM0_CALIBRATE_PPB_QUANTA (1000)
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enum rtc_sam0_counter_mode {
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COUNTER_MODE_0,
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COUNTER_MODE_1,
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COUNTER_MODE_2,
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};
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struct rtc_sam0_config {
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Rtc *regs;
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enum rtc_sam0_counter_mode mode;
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uint16_t prescaler;
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volatile uint32_t *mclk;
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uint32_t mclk_mask;
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uint32_t gclk_gen;
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uint16_t gclk_id;
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bool has_gclk;
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bool has_osc32kctrl;
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uint8_t osc32_src;
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uint32_t evt_ctrl_msk;
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#ifdef CONFIG_RTC_ALARM
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uint8_t alarms_count;
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#endif /* CONFIG_RTC_ALARM */
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#ifdef CONFIG_RTC_CALIBRATION
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int32_t cal_constant;
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#endif
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};
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struct rtc_sam0_data_cb {
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rtc_alarm_callback cb;
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void *cb_data;
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};
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struct rtc_sam0_data {
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struct k_spinlock lock;
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#ifdef CONFIG_RTC_ALARM
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struct rtc_sam0_data_cb *const alarms;
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#endif /* CONFIG_RTC_ALARM */
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};
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static inline void rtc_sam0_sync(Rtc *rtc)
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{
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/* Wait for synchronization */
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#ifdef MCLK
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while (rtc->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_MASK) {
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}
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#else
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while (rtc->MODE0.STATUS.reg & RTC_STATUS_SYNCBUSY) {
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}
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#endif
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}
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static int rtc_sam0_set_time(const struct device *dev, const struct rtc_time *timeptr)
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{
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const struct rtc_sam0_config *cfg = dev->config;
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struct rtc_sam0_data *data = dev->data;
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RtcMode2 *regs = &cfg->regs->MODE2;
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uint32_t datetime = 0;
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if (rtc_utils_validate_rtc_time(timeptr, RTC_SAM0_TIME_MASK) == false) {
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return -EINVAL;
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}
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datetime |= RTC_MODE2_CLOCK_SECOND(timeptr->tm_sec);
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datetime |= RTC_MODE2_CLOCK_MINUTE(timeptr->tm_min);
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datetime |= RTC_MODE2_CLOCK_HOUR(timeptr->tm_hour);
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datetime |= RTC_MODE2_CLOCK_DAY(timeptr->tm_mday);
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datetime |= RTC_MODE2_CLOCK_MONTH(timeptr->tm_mon + 1);
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datetime |= RTC_MODE2_CLOCK_YEAR(timeptr->tm_year - 99);
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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#ifdef MCLK
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regs->CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
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rtc_sam0_sync(cfg->regs);
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regs->CLOCK.reg = datetime;
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regs->CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
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#else
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regs->CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE;
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rtc_sam0_sync(cfg->regs);
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regs->CLOCK.reg = datetime;
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regs->CTRL.reg |= RTC_MODE0_CTRL_ENABLE;
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#endif
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int rtc_sam0_get_time(const struct device *dev, struct rtc_time *timeptr)
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{
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const struct rtc_sam0_config *cfg = dev->config;
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RTC_MODE2_CLOCK_Type calendar = cfg->regs->MODE2.CLOCK;
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timeptr->tm_sec = calendar.bit.SECOND;
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timeptr->tm_min = calendar.bit.MINUTE;
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timeptr->tm_hour = calendar.bit.HOUR;
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timeptr->tm_mday = calendar.bit.DAY;
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timeptr->tm_mon = calendar.bit.MONTH - 1;
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timeptr->tm_year = calendar.bit.YEAR + 99;
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timeptr->tm_wday = -1;
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timeptr->tm_yday = -1;
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timeptr->tm_isdst = -1;
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timeptr->tm_nsec = 0;
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LOG_DBG("D/M/Y H:M:S %02d/%02d/%02d %02d:%02d:%02d",
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timeptr->tm_mday, timeptr->tm_mon + 1, timeptr->tm_year - 99,
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timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
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return 0;
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}
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#ifdef CONFIG_RTC_ALARM
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static inline uint32_t rtc_sam0_datetime_from_tm(const struct rtc_time *timeptr,
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uint32_t mask)
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{
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uint32_t datetime = 0;
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if (mask & RTC_ALARM_TIME_MASK_SECOND) {
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datetime |= RTC_MODE2_CLOCK_SECOND(timeptr->tm_sec);
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}
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if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
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datetime |= RTC_MODE2_CLOCK_MINUTE(timeptr->tm_min);
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}
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if (mask & RTC_ALARM_TIME_MASK_HOUR) {
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datetime |= RTC_MODE2_CLOCK_HOUR(timeptr->tm_hour);
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}
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if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
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datetime |= RTC_MODE2_CLOCK_DAY(timeptr->tm_mday);
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}
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if (mask & RTC_ALARM_TIME_MASK_MONTH) {
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datetime |= RTC_MODE2_CLOCK_MONTH(timeptr->tm_mon + 1);
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}
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if (mask & RTC_ALARM_TIME_MASK_YEAR) {
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datetime |= RTC_MODE2_CLOCK_YEAR(timeptr->tm_year - 99);
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}
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return datetime;
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}
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static inline void rtc_sam0_tm_from_datetime(struct rtc_time *timeptr, uint32_t mask,
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RTC_MODE2_ALARM_Type calendar)
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{
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memset(timeptr, 0x00, sizeof(struct rtc_time));
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if (mask & RTC_ALARM_TIME_MASK_SECOND) {
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timeptr->tm_sec = calendar.bit.SECOND;
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}
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if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
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timeptr->tm_min = calendar.bit.MINUTE;
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}
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if (mask & RTC_ALARM_TIME_MASK_HOUR) {
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timeptr->tm_hour = calendar.bit.HOUR;
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}
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if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
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timeptr->tm_mday = calendar.bit.DAY;
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}
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if (mask & RTC_ALARM_TIME_MASK_MONTH) {
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timeptr->tm_mon = calendar.bit.MONTH - 1;
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}
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if (mask & RTC_ALARM_TIME_MASK_YEAR) {
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timeptr->tm_year = calendar.bit.YEAR + 99;
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}
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timeptr->tm_wday = -1;
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timeptr->tm_yday = -1;
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timeptr->tm_isdst = -1;
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timeptr->tm_nsec = 0;
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}
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static inline uint32_t rtc_sam0_alarm_msk_from_mask(uint32_t mask)
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{
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uint32_t alarm_mask = 0;
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if (mask & RTC_ALARM_TIME_MASK_SECOND) {
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alarm_mask = RTC_MODE2_MASK_SEL_SS_Val;
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}
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if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
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alarm_mask = RTC_MODE2_MASK_SEL_MMSS_Val;
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}
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if (mask & RTC_ALARM_TIME_MASK_HOUR) {
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alarm_mask = RTC_MODE2_MASK_SEL_HHMMSS_Val;
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}
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if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
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alarm_mask = RTC_MODE2_MASK_SEL_DDHHMMSS_Val;
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}
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if (mask & RTC_ALARM_TIME_MASK_MONTH) {
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alarm_mask = RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val;
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}
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if (mask & RTC_ALARM_TIME_MASK_YEAR) {
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alarm_mask = RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val;
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}
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return alarm_mask;
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}
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static inline uint32_t rtc_sam0_mask_from_alarm_msk(uint32_t alarm_mask)
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{
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uint32_t mask = 0;
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switch (alarm_mask) {
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case RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val:
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mask |= RTC_ALARM_TIME_MASK_YEAR;
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__fallthrough;
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case RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val:
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mask |= RTC_ALARM_TIME_MASK_MONTH;
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__fallthrough;
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case RTC_MODE2_MASK_SEL_DDHHMMSS_Val:
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mask |= RTC_ALARM_TIME_MASK_MONTHDAY;
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__fallthrough;
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case RTC_MODE2_MASK_SEL_HHMMSS_Val:
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mask |= RTC_ALARM_TIME_MASK_HOUR;
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__fallthrough;
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case RTC_MODE2_MASK_SEL_MMSS_Val:
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mask |= RTC_ALARM_TIME_MASK_MINUTE;
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__fallthrough;
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case RTC_MODE2_MASK_SEL_SS_Val:
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mask |= RTC_ALARM_TIME_MASK_SECOND;
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break;
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default:
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break;
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}
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return mask;
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}
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static int rtc_sam0_alarm_get_supported_fields(const struct device *dev, uint16_t id,
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uint16_t *mask)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(id);
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*mask = RTC_SAM0_TIME_MASK;
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return 0;
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}
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static int rtc_sam0_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
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const struct rtc_time *timeptr)
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{
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const struct rtc_sam0_config *cfg = dev->config;
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struct rtc_sam0_data *data = dev->data;
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RtcMode2 *regs = &cfg->regs->MODE2;
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uint32_t mask_supported = RTC_SAM0_TIME_MASK;
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uint32_t datetime;
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uint32_t alarm_msk;
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if (BIT(id) > RTC_MODE2_INTFLAG_ALARM_Msk) {
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return -EINVAL;
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}
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if ((mask > 0) && (timeptr == NULL)) {
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return -EINVAL;
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}
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if (mask & ~mask_supported) {
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return -EINVAL;
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}
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if (rtc_utils_validate_rtc_time(timeptr, mask) == false) {
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return -EINVAL;
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}
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datetime = rtc_sam0_datetime_from_tm(timeptr, mask);
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alarm_msk = rtc_sam0_alarm_msk_from_mask(mask);
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LOG_DBG("S: datetime: %d, mask: %d", datetime, alarm_msk);
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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irq_disable(DT_INST_IRQN(0));
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rtc_sam0_sync(cfg->regs);
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regs->Mode2Alarm[id].ALARM.reg = datetime;
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regs->Mode2Alarm[id].MASK.reg = RTC_MODE2_MASK_SEL(alarm_msk);
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regs->INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(BIT(id));
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irq_enable(DT_INST_IRQN(0));
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int rtc_sam0_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
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struct rtc_time *timeptr)
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{
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const struct rtc_sam0_config *cfg = dev->config;
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struct rtc_sam0_data *data = dev->data;
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RtcMode2 *regs = &cfg->regs->MODE2;
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RTC_MODE2_ALARM_Type datetime;
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uint32_t alarm_msk;
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if (BIT(id) > RTC_MODE2_INTFLAG_ALARM_Msk) {
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return -EINVAL;
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}
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if ((mask == NULL) || (timeptr == NULL)) {
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return -EINVAL;
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}
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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rtc_sam0_sync(cfg->regs);
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datetime = regs->Mode2Alarm[id].ALARM;
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alarm_msk = regs->Mode2Alarm[id].MASK.reg;
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LOG_DBG("G: datetime: %d, mask: %d", datetime.reg, alarm_msk);
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k_spin_unlock(&data->lock, key);
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*mask = rtc_sam0_mask_from_alarm_msk(alarm_msk);
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rtc_sam0_tm_from_datetime(timeptr, *mask, datetime);
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return 0;
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}
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static int rtc_sam0_alarm_is_pending(const struct device *dev, uint16_t id)
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{
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const struct rtc_sam0_config *cfg = dev->config;
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struct rtc_sam0_data *data = dev->data;
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RtcMode2 *regs = &cfg->regs->MODE2;
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if (BIT(id) > RTC_MODE2_INTFLAG_ALARM_Msk) {
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return -EINVAL;
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}
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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if ((regs->INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM(BIT(id))) == 0) {
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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regs->INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(BIT(id));
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k_spin_unlock(&data->lock, key);
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return 1;
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}
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static int rtc_sam0_alarm_set_callback(const struct device *dev, uint16_t id,
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rtc_alarm_callback callback, void *user_data)
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{
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const struct rtc_sam0_config *cfg = dev->config;
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struct rtc_sam0_data *data = dev->data;
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RtcMode2 *regs = &cfg->regs->MODE2;
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if (BIT(id) > RTC_MODE2_INTFLAG_ALARM_Msk) {
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return -EINVAL;
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}
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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data->alarms[id].cb = callback;
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data->alarms[id].cb_data = user_data;
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if (callback) {
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regs->INTENSET.reg = RTC_MODE2_INTENSET_ALARM(BIT(id));
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} else {
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regs->INTENCLR.reg = RTC_MODE2_INTENCLR_ALARM(BIT(id));
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}
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static void rtc_sam0_isr(const struct device *dev)
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{
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const struct rtc_sam0_config *cfg = dev->config;
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struct rtc_sam0_data *data = dev->data;
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RtcMode2 *regs = &cfg->regs->MODE2;
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uint32_t int_flags = regs->INTFLAG.reg;
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for (int i = 0; i < cfg->alarms_count; ++i) {
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if (int_flags & RTC_MODE2_INTFLAG_ALARM(BIT(i))) {
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if (data->alarms[i].cb != NULL) {
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data->alarms[i].cb(dev, i, data->alarms[i].cb_data);
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}
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}
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}
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regs->INTFLAG.reg |= int_flags;
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}
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#endif /* CONFIG_RTC_ALARM */
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#ifdef CONFIG_RTC_CALIBRATION
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static int rtc_sam0_set_calibration(const struct device *dev, int32_t calibration)
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{
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const struct rtc_sam0_config *cfg = dev->config;
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RtcMode2 *regs = &cfg->regs->MODE2;
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int32_t correction = calibration / (1000000000 / cfg->cal_constant);
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uint32_t abs_correction = abs(correction);
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LOG_DBG("Correction: %d, Absolute: %d, Calibration: %d",
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correction, abs_correction, calibration);
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if (abs_correction == 0) {
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regs->FREQCORR.reg = 0;
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return 0;
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}
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if (abs_correction > RTC_SAM0_CALIBRATE_PPB_MAX) {
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LOG_ERR("The calibration %d result in an out of range value %d",
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calibration, abs_correction);
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return -EINVAL;
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}
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rtc_sam0_sync(cfg->regs);
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regs->FREQCORR.reg = RTC_FREQCORR_VALUE(abs_correction)
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| (correction < 0 ? RTC_FREQCORR_SIGN : 0);
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LOG_DBG("W REG: 0x%02x", regs->FREQCORR.reg);
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return 0;
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}
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static int rtc_sam0_get_calibration(const struct device *dev, int32_t *calibration)
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{
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const struct rtc_sam0_config *cfg = dev->config;
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RtcMode2 *regs = &cfg->regs->MODE2;
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int32_t correction;
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if (calibration == NULL) {
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return -EINVAL;
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}
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correction = regs->FREQCORR.bit.VALUE;
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if (correction == 0) {
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*calibration = 0;
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} else {
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*calibration = (correction * 1000000000) / cfg->cal_constant;
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}
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if (regs->FREQCORR.bit.SIGN) {
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*calibration *= -1;
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}
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LOG_DBG("R REG: 0x%02x", regs->FREQCORR.reg);
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return 0;
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}
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#endif /* CONFIG_RTC_CALIBRATION */
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static int rtc_sam0_init(const struct device *dev)
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{
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const struct rtc_sam0_config *cfg = dev->config;
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RtcMode0 *regs = &cfg->regs->MODE0;
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LOG_DBG("Counter Mode %d selected", cfg->mode);
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LOG_DBG("gclk_id: %d, gclk_gen: %d, prescaler: %d, osc32k: %d",
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cfg->gclk_id, cfg->gclk_gen, cfg->prescaler, cfg->osc32_src);
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*cfg->mclk |= cfg->mclk_mask;
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#ifdef MCLK
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if (cfg->has_gclk) {
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GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
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| GCLK_PCHCTRL_GEN(cfg->gclk_gen);
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}
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#else
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
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| GCLK_CLKCTRL_GEN(cfg->gclk_gen)
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| GCLK_CLKCTRL_ID(cfg->gclk_id);
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#endif
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rtc_sam0_sync(cfg->regs);
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#ifdef MCLK
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if (cfg->has_osc32kctrl) {
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OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL(cfg->osc32_src);
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}
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#endif
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rtc_sam0_sync(cfg->regs);
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regs->EVCTRL.reg = (cfg->evt_ctrl_msk & RTC_MODE0_EVCTRL_MASK);
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#ifdef MCLK
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regs->CTRLA.reg = RTC_MODE0_CTRLA_ENABLE
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| RTC_MODE0_CTRLA_COUNTSYNC
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| RTC_MODE0_CTRLA_MODE(cfg->mode)
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| RTC_MODE0_CTRLA_PRESCALER(cfg->prescaler + 1);
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#else
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regs->CTRL.reg = RTC_MODE0_CTRL_ENABLE
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| RTC_MODE0_CTRL_MODE(cfg->mode)
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| RTC_MODE0_CTRL_PRESCALER(cfg->prescaler);
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#endif
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regs->INTFLAG.reg = 0;
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#ifdef CONFIG_RTC_ALARM
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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rtc_sam0_isr,
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DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQN(0));
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#endif
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return 0;
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}
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static DEVICE_API(rtc, rtc_sam0_driver_api) = {
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.set_time = rtc_sam0_set_time,
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.get_time = rtc_sam0_get_time,
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#ifdef CONFIG_RTC_ALARM
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.alarm_get_supported_fields = rtc_sam0_alarm_get_supported_fields,
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.alarm_set_time = rtc_sam0_alarm_set_time,
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.alarm_get_time = rtc_sam0_alarm_get_time,
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.alarm_is_pending = rtc_sam0_alarm_is_pending,
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.alarm_set_callback = rtc_sam0_alarm_set_callback,
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#endif /* CONFIG_RTC_ALARM */
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#ifdef CONFIG_RTC_CALIBRATION
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.set_calibration = rtc_sam0_set_calibration,
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.get_calibration = rtc_sam0_get_calibration,
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#endif /* CONFIG_RTC_CALIBRATION */
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};
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#define ASSIGNED_CLOCKS_CELL_BY_NAME \
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ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
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#define RTC_SAM0_GCLK(n) \
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COND_CODE_1(DT_INST_CLOCKS_HAS_NAME(n, gclk), \
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( \
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.has_gclk = true, \
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.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen), \
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.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id) \
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), \
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( \
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.has_gclk = false, \
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.gclk_gen = 0, \
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.gclk_id = 0 \
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))
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#define RTC_SAM0_OSC32KCTRL(n) \
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COND_CODE_1(DT_INST_CLOCKS_HAS_NAME(n, osc32kctrl), \
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( \
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.has_osc32kctrl = true, \
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.osc32_src = ASSIGNED_CLOCKS_CELL_BY_NAME(n, osc32kctrl, src) \
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), \
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( \
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.has_osc32kctrl = false, \
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.osc32_src = 0 \
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))
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#define RTC_SAM0_DEVICE(n) \
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BUILD_ASSERT(DT_INST_NODE_HAS_PROP(n, counter_mode), \
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"sam0:rtc: Missing counter-mode devicetree property"); \
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BUILD_ASSERT(DT_INST_NODE_HAS_PROP(n, prescaler), \
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"sam0:rtc: Missing prescaler devicetree property"); \
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\
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static const struct rtc_sam0_config rtc_sam0_config_##n = { \
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.regs = (Rtc *)DT_INST_REG_ADDR(n), \
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.mode = DT_INST_ENUM_IDX(n, counter_mode), \
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.prescaler = DT_INST_ENUM_IDX(n, prescaler), \
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.evt_ctrl_msk = DT_INST_PROP(n, event_control_msk), \
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RTC_SAM0_GCLK(n), \
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RTC_SAM0_OSC32KCTRL(n), \
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.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n), \
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.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(n, bit), \
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IF_ENABLED(CONFIG_RTC_ALARM, ( \
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.alarms_count = DT_INST_PROP(n, alarms_count), \
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)) \
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IF_ENABLED(CONFIG_RTC_CALIBRATION, ( \
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.cal_constant = DT_INST_PROP(n, cal_constant), \
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)) \
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}; \
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\
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IF_ENABLED(CONFIG_RTC_ALARM, ( \
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static struct rtc_sam0_data_cb \
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rtc_sam0_data_cb_##n[DT_INST_PROP(n, alarms_count)] = {}; \
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)) \
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\
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static struct rtc_sam0_data rtc_sam0_data_##n = { \
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IF_ENABLED(CONFIG_RTC_ALARM, ( \
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.alarms = rtc_sam0_data_cb_##n, \
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)) \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, rtc_sam0_init, \
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NULL, \
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&rtc_sam0_data_##n, \
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&rtc_sam0_config_##n, POST_KERNEL, \
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CONFIG_RTC_INIT_PRIORITY, \
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&rtc_sam0_driver_api); \
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DT_INST_FOREACH_STATUS_OKAY(RTC_SAM0_DEVICE);
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/* clang-format on */
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