1146574b67
Added support to gicv3 driver to utilize the extended SPI MMIO registers introduced in GICv3.1 for the extended SPI range. Documentation for the Extended Shared Peripheral Interrupts extension can be found in the ARM General Interrupt Controller Architecture Specification: https://developer.arm.com/documentation/ihi0069/latest/ Signed-off-by: Adam Openshaw <quic_adamo@quicinc.com>
74 lines
2.9 KiB
C
74 lines
2.9 KiB
C
/*
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* Copyright 2020 Broadcom
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_INTC_GIC_COMMON_PRIV_H_
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#define ZEPHYR_INCLUDE_DRIVERS_INTC_GIC_COMMON_PRIV_H_
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/* Offsets from GICD base or GICR(n) SGI_base */
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#define GIC_DIST_IGROUPR 0x0080
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#define GIC_DIST_ISENABLER 0x0100
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#define GIC_DIST_ICENABLER 0x0180
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#define GIC_DIST_ISPENDR 0x0200
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#define GIC_DIST_ICPENDR 0x0280
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#define GIC_DIST_ISACTIVER 0x0300
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#define GIC_DIST_ICACTIVER 0x0380
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#define GIC_DIST_IPRIORITYR 0x0400
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#define GIC_DIST_ITARGETSR 0x0800
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#define GIC_DIST_ICFGR 0x0c00
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#define GIC_DIST_IGROUPMODR 0x0d00
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#define GIC_DIST_SGIR 0x0f00
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/* GICv3.1 Support for Extended SPI Range */
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#define GIC_ESPI_START 4096
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#define GIC_ESPI_END 5119
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#define GIC_DIST_IGROUPRnE 0x1000
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#define GIC_DIST_ISENABLERnE 0x1200
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#define GIC_DIST_ICENABLERnE 0x1400
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#define GIC_DIST_ISPENDRnE 0x1600
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#define GIC_DIST_ICPENDRnE 0x1800
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#define GIC_DIST_ISACTIVERnE 0x1a00
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#define GIC_DIST_ICACTIVERnE 0x1c00
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#define GIC_DIST_IPRIORITYRnE 0x2000
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#define GIC_DIST_ICFGRnE 0x3000
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#define GIC_DIST_IGROUPMODRnE 0x3400
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/* GICD GICR common access macros */
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#define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4)
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#define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4)
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#define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4)
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#define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4)
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#define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4)
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#define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n)
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#define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4)
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#define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4)
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#define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4)
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/* GICD Extended SPI (GICv3.1) common access macros */
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#define IGROUPRnE(base, n) (base + GIC_DIST_IGROUPRnE + (n) * 4)
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#define ISENABLERnE(base, n) (base + GIC_DIST_ISENABLERnE + (n) * 4)
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#define ICENABLERnE(base, n) (base + GIC_DIST_ICENABLERnE + (n) * 4)
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#define ISPENDRnE(base, n) (base + GIC_DIST_ISPENDRnE + (n) * 4)
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#define ICPENDRnE(base, n) (base + GIC_DIST_ICPENDRnE + (n) * 4)
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#define IPRIORITYRnE(base, n) (base + GIC_DIST_IPRIORITYRnE + n)
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#define ICFGRnE(base, n) (base + GIC_DIST_ICFGRnE + (n) * 4)
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#define IGROUPMODRnE(base, n) (base + GIC_DIST_IGROUPMODRnE + (n) * 4)
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/*
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* selects redistributor SGI_base for current core for PPI and SGI
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* selects distributor base for SPI
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* The macro translates to distributor base for GICv2 and GICv1
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*/
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#if CONFIG_GIC_VER <= 2
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#define GET_DIST_BASE(intid) GIC_DIST_BASE
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#define GIC_IS_ESPI(intid) 0
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#else
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#define GET_DIST_BASE(intid) \
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((intid < GIC_SPI_INT_BASE) ? (gic_get_rdist() + GICR_SGI_BASE_OFF) : GIC_DIST_BASE)
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#define GIC_IS_ESPI(intid) ((intid >= GIC_ESPI_START) && (intid <= GIC_ESPI_END))
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#endif
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#endif /* ZEPHYR_INCLUDE_DRIVERS_INTC_GIC_COMMON_PRIV_H */
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