dbd0ac40ce
Add indirect CSR access to access CLIC register to satisfy the current CLIC spec (Version v0.9, 2024-06-28: Draf). Add CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS for legacy CLIC implementation with memory-mapped CLIC register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
341 lines
10 KiB
C
341 lines
10 KiB
C
/*
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* Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
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* Copyright (c) 2025 Andes Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Driver for Core Local Interrupt Controller
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/arch/riscv/csr.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/interrupt_controller/riscv_clic.h>
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#include "intc_clic.h"
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#if DT_HAS_COMPAT_STATUS_OKAY(riscv_clic)
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#define DT_DRV_COMPAT riscv_clic
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#elif DT_HAS_COMPAT_STATUS_OKAY(nuclei_eclic)
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#define DT_DRV_COMPAT nuclei_eclic
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#else
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#error "Unknown CLIC controller compatible for this configuration"
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#endif
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struct clic_data {
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uint8_t nlbits;
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uint8_t intctlbits;
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};
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struct clic_config {
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mem_addr_t base;
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};
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struct pmp_stack_guard_key_t {
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unsigned long mstatus;
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unsigned int irq_key;
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};
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/*
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* M-mode CLIC memory-mapped registers are accessible only in M-mode.
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* Temporarily disable the PMP stack guard (set mstatus.MPRV = 0) to configure
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* CLIC registers, then restore the PMP stack guard using these functions.
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*/
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static ALWAYS_INLINE void disable_pmp_stack_guard(struct pmp_stack_guard_key_t *key)
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{
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if (IS_ENABLED(CONFIG_PMP_STACK_GUARD)) {
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key->irq_key = irq_lock();
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key->mstatus = csr_read_clear(mstatus, MSTATUS_MPRV);
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} else {
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ARG_UNUSED(key);
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}
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}
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static ALWAYS_INLINE void restore_pmp_stack_guard(struct pmp_stack_guard_key_t key)
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{
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if (IS_ENABLED(CONFIG_PMP_STACK_GUARD)) {
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csr_write(mstatus, key.mstatus);
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irq_unlock(key.irq_key);
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} else {
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ARG_UNUSED(key);
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}
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}
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static ALWAYS_INLINE void write_clic32(const struct device *dev, uint32_t offset, uint32_t value)
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{
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const struct clic_config *config = dev->config;
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mem_addr_t reg_addr = config->base + offset;
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struct pmp_stack_guard_key_t key;
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disable_pmp_stack_guard(&key);
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sys_write32(value, reg_addr);
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restore_pmp_stack_guard(key);
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}
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static ALWAYS_INLINE uint32_t read_clic32(const struct device *dev, uint32_t offset)
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{
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const struct clic_config *config = dev->config;
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mem_addr_t reg_addr = config->base + offset;
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struct pmp_stack_guard_key_t key;
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uint32_t reg;
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disable_pmp_stack_guard(&key);
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reg = sys_read32(reg_addr);
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restore_pmp_stack_guard(key);
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return reg;
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}
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static ALWAYS_INLINE void write_clic8(const struct device *dev, uint32_t offset, uint8_t value)
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{
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const struct clic_config *config = dev->config;
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mem_addr_t reg_addr = config->base + offset;
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struct pmp_stack_guard_key_t key;
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disable_pmp_stack_guard(&key);
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sys_write8(value, reg_addr);
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restore_pmp_stack_guard(key);
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}
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static ALWAYS_INLINE uint8_t read_clic8(const struct device *dev, uint32_t offset)
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{
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const struct clic_config *config = dev->config;
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mem_addr_t reg_addr = config->base + offset;
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struct pmp_stack_guard_key_t key;
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uint32_t reg;
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disable_pmp_stack_guard(&key);
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reg = sys_read8(reg_addr);
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restore_pmp_stack_guard(key);
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return reg;
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}
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/**
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* @brief Enable interrupt
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*/
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void riscv_clic_irq_enable(uint32_t irq)
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{
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if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
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const struct device *dev = DEVICE_DT_INST_GET(0);
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union CLICINTIE clicintie = {.b = {.IE = 0x1}};
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write_clic8(dev, CLIC_INTIE(irq), clicintie.w);
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} else {
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csr_write(CSR_MISELECT, CLIC_INTIE(irq));
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csr_set(CSR_MIREG2, BIT(irq % 32));
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}
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}
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/**
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* @brief Disable interrupt
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*/
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void riscv_clic_irq_disable(uint32_t irq)
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{
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if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
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const struct device *dev = DEVICE_DT_INST_GET(0);
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union CLICINTIE clicintie = {.b = {.IE = 0x0}};
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write_clic8(dev, CLIC_INTIE(irq), clicintie.w);
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} else {
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csr_write(CSR_MISELECT, CLIC_INTIE(irq));
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csr_clear(CSR_MIREG2, BIT(irq % 32));
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}
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}
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/**
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* @brief Get enable status of interrupt
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*/
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int riscv_clic_irq_is_enabled(uint32_t irq)
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{
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int is_enabled = 0;
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if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
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const struct device *dev = DEVICE_DT_INST_GET(0);
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union CLICINTIE clicintie = {.w = read_clic8(dev, CLIC_INTIE(irq))};
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is_enabled = clicintie.b.IE;
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} else {
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csr_write(CSR_MISELECT, CLIC_INTIE(irq));
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is_enabled = csr_read(CSR_MIREG2) & BIT(irq % 32);
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}
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return !!is_enabled;
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}
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/**
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* @brief Set priority and level of interrupt
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*/
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void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags)
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{
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const struct device *dev = DEVICE_DT_INST_GET(0);
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const struct clic_data *data = dev->data;
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/*
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* Set the interrupt level and the interrupt priority.
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* Examples of mcliccfg settings:
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* CLICINTCTLBITS mnlbits clicintctl[i] interrupt levels
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* 0 2 ........ 255
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* 1 2 l....... 127,255
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* 2 2 ll...... 63,127,191,255
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* 3 3 lll..... 31,63,95,127,159,191,223,255
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* 4 1 lppp.... 127,255
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* "." bits are non-existent bits for level encoding, assumed to be 1
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* "l" bits are available variable bits in level specification
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* "p" bits are available variable bits in priority specification
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*/
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const uint8_t max_level = BIT_MASK(data->nlbits);
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const uint8_t max_prio = BIT_MASK(data->intctlbits - data->nlbits);
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uint8_t intctrl = (MIN(pri, max_prio) << (8U - data->intctlbits)) |
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(MIN(pri, max_level) << (8U - data->nlbits)) |
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BIT_MASK(8U - data->intctlbits);
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if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
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write_clic8(dev, CLIC_INTCTRL(irq), intctrl);
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} else {
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uint32_t clicintctl, bit_offset = 8 * (irq % 4);
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csr_write(CSR_MISELECT, CLIC_INTCTRL(irq));
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clicintctl = csr_read(CSR_MIREG);
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clicintctl &= ~GENMASK(bit_offset + 7, bit_offset);
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clicintctl |= intctrl << bit_offset;
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csr_write(CSR_MIREG, clicintctl);
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}
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/* Set the IRQ operates in machine mode, non-vectoring and the trigger type. */
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union CLICINTATTR clicattr = {.b = {.mode = 0x3, .shv = 0x0, .trg = flags & BIT_MASK(3)}};
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if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
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write_clic8(dev, CLIC_INTATTR(irq), clicattr.w);
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} else {
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uint32_t clicintattr, bit_offset = 8 * (irq % 4);
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csr_write(CSR_MISELECT, CLIC_INTATTR(irq));
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clicintattr = csr_read(CSR_MIREG2);
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clicintattr &= ~GENMASK(bit_offset + 7, bit_offset);
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clicintattr |= clicattr.w << bit_offset;
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csr_write(CSR_MIREG2, clicintattr);
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}
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}
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/**
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* @brief Set vector mode of interrupt
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*/
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void riscv_clic_irq_vector_set(uint32_t irq)
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{
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if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
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const struct device *dev = DEVICE_DT_INST_GET(0);
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union CLICINTATTR clicattr = {.w = read_clic8(dev, CLIC_INTATTR(irq))};
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/* Set Selective Hardware Vectoring. */
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clicattr.b.shv = 1;
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write_clic8(dev, CLIC_INTATTR(irq), clicattr.w);
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} else {
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uint32_t clicintattr, bit_offset = 8 * (irq % 4);
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union CLICINTATTR clicattr = {.b = {.shv = 1}};
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csr_write(CSR_MISELECT, CLIC_INTATTR(irq));
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clicintattr = csr_read(CSR_MIREG2);
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clicintattr |= clicattr.w << bit_offset;
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csr_write(CSR_MIREG2, clicintattr);
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}
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}
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/**
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* @brief Set pending bit of an interrupt
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*/
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void riscv_clic_irq_set_pending(uint32_t irq)
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{
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if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
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const struct device *dev = DEVICE_DT_INST_GET(0);
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union CLICINTIP clicintip = {.b = {.IP = 0x1}};
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write_clic8(dev, CLIC_INTIP(irq), clicintip.w);
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} else {
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csr_write(CSR_MISELECT, CLIC_INTIP(irq));
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csr_set(CSR_MIREG, BIT(irq % 32));
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}
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}
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static int clic_init(const struct device *dev)
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{
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struct clic_data *data = dev->data;
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if (IS_ENABLED(CONFIG_NUCLEI_ECLIC)) {
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/* Configure the interrupt level threshold. */
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union CLICMTH clicmth = {.b = {.mth = 0x0}};
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write_clic32(dev, CLIC_MTH, clicmth.qw);
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/* Detect the number of bits for the clicintctl register. */
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union CLICINFO clicinfo = {.qw = read_clic32(dev, CLIC_INFO)};
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data->intctlbits = clicinfo.b.intctlbits;
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if (data->nlbits > data->intctlbits) {
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data->nlbits = data->intctlbits;
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}
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} else {
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/* Configure the interrupt level threshold by CSR mintthresh. */
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csr_write(CSR_MINTTHRESH, 0x0);
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}
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if (IS_ENABLED(CONFIG_CLIC_SMCLICCONFIG_EXT)) {
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if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
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/* Configure the number of bits assigned to interrupt levels. */
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union CLICCFG cliccfg = {.qw = read_clic32(dev, CLIC_CFG)};
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cliccfg.w.nlbits = data->nlbits;
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write_clic32(dev, CLIC_CFG, cliccfg.qw);
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} else {
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csr_write(CSR_MISELECT, CLIC_CFG);
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union CLICCFG cliccfg = {.qw = csr_read(CSR_MIREG)};
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cliccfg.w.nlbits = data->nlbits;
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csr_write(CSR_MIREG, cliccfg.qw);
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}
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}
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if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
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/* Reset all interrupt control register. */
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for (int i = 0; i < CONFIG_NUM_IRQS; i++) {
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write_clic32(dev, CLIC_CTRL(i), 0);
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}
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} else {
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/* Reset all clicintip, clicintie register. */
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for (int i = 0; i < CONFIG_NUM_IRQS; i += 32) {
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csr_write(CSR_MISELECT, CLIC_INTIP(i));
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csr_write(CSR_MIREG, 0);
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csr_write(CSR_MIREG2, 0);
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}
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/* Reset all clicintctl, clicintattr register. */
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for (int i = 0; i < CONFIG_NUM_IRQS; i += 4) {
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csr_write(CSR_MISELECT, CLIC_INTCTRL(i));
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csr_write(CSR_MIREG, 0);
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csr_write(CSR_MIREG2, 0);
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}
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}
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return 0;
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}
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#define CLIC_INTC_DATA_INIT(n) \
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static struct clic_data clic_data_##n = { \
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.nlbits = CONFIG_CLIC_PARAMETER_MNLBITS, \
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.intctlbits = CONFIG_CLIC_PARAMETER_INTCTLBITS, \
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};
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#define CLIC_INTC_CONFIG_INIT(n) \
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const static struct clic_config clic_config_##n = { \
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.base = COND_CODE_1(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS, \
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(DT_REG_ADDR(DT_DRV_INST(n))), (0)), \
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};
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#define CLIC_INTC_DEVICE_INIT(n) \
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CLIC_INTC_DATA_INIT(n) \
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CLIC_INTC_CONFIG_INIT(n) \
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DEVICE_DT_INST_DEFINE(n, &clic_init, NULL, &clic_data_##n, &clic_config_##n, PRE_KERNEL_1, \
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CONFIG_INTC_INIT_PRIORITY, NULL);
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DT_INST_FOREACH_STATUS_OKAY(CLIC_INTC_DEVICE_INIT)
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