a7f9ebe9d5
This patch is used to provide clic(eclic) in 64 bit riscv cpu support, since in 64 bit riscv cpu, the clic irq table entry is also 64 bit, so we need to use ld/sd to do irq entry load and store Signed-off-by: Huaqi Fang <578567190@qq.com>
104 lines
2.2 KiB
ArmAsm
104 lines
2.2 KiB
ArmAsm
/*
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* Copyright (c) 2024 Baumer Electric AG
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Assembler-hooks specific to RISC-V Core Local Interrupt Controller
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*/
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#include <zephyr/arch/cpu.h>
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#include "intc_clic.h"
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#ifdef CONFIG_64BIT
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/* register-wide load/store based on ld/sd (XLEN = 64) */
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.macro lr, rd, mem
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ld \rd, \mem
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.endm
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.macro sr, rs, mem
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sd \rs, \mem
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.endm
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#else
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/* register-wide load/store based on lw/sw (XLEN = 32) */
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.macro lr, rd, mem
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lw \rd, \mem
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.endm
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.macro sr, rs, mem
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sw \rs, \mem
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.endm
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#endif
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GTEXT(__soc_handle_irq)
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/*
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* In an CLIC, pending interrupts don't have to be cleared by hand.
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* In vectored mode, interrupts are cleared automatically.
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* In non-vectored mode, interrupts are cleared when writing the mnxti register (done in
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* __soc_handle_all_irqs).
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* Thus this function can directly return.
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*/
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SECTION_FUNC(exception.other, __soc_handle_irq)
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ret
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GTEXT(__soc_handle_all_irqs)
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#ifdef CONFIG_TRACING
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/* imports */
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GTEXT(sys_trace_isr_enter)
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GTEXT(sys_trace_isr_exit)
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#endif
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/*
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* This function services and clears all pending interrupts for an CLIC in non-vectored mode.
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*/
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SECTION_FUNC(exception.other, __soc_handle_all_irqs)
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addi sp, sp, -16
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sr ra, 0(sp)
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/* Read and clear mnxti to get highest current interrupt and enable interrupts. Will return
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* original interrupt if no others appear. */
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csrrci a0, CSR_MNXTI, MSTATUS_IEN
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beqz a0, irq_done /* Check if original interrupt vanished. */
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irq_loop:
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#ifdef CONFIG_TRACING_ISR
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call sys_trace_isr_enter
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#endif
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/* Call corresponding registered function in _sw_isr_table. a0 is offset in pointer with
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* the mtvt, sw irq table is 2-pointer wide -> shift by one. */
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csrr t0, CSR_MTVT
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sub a0, a0, t0
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la t0, _sw_isr_table
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slli a0, a0, (1)
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add t0, t0, a0
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/* Load argument in a0 register */
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lr a0, 0(t0)
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/* Load ISR function address in register t1 */
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lr t1, RV_REGSIZE(t0)
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/* Call ISR function */
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jalr ra, t1, 0
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#ifdef CONFIG_TRACING_ISR
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call sys_trace_isr_exit
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#endif
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/* Read and clear mnxti to get highest current interrupt and enable interrupts. */
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csrrci a0, CSR_MNXTI, MSTATUS_IEN
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bnez a0, irq_loop
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irq_done:
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lr ra, 0(sp)
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addi sp, sp, 16
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ret
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