affecd1839
The Ethernet device model consists of multiple subsystem components, such
as MDIO, PHY, MAC and PTP_CLOCK. These components are mapped into a single
PCIe BAR location with same base address.
This platform driver retrieves the MMIO mapping details and provides a
framework to share it with all the child subsystem components. This
approach avoid the duplicate remapping, ensures efficient re-use of
MMIO mappings across related devices.
Example device tree structure for first ethernet instance:
parent0: parent0 {
compatible = "intel,eth-plat";
interrupt-parent = <&intc>;
vendor-id = <0x8086>;
device-id = <0xXXXX>;
igc0: igc0 {
compatible = "intel,igc-mac";
/*
* MAC specific properties.
*/
status = "okay";
};
mdio0: mdio0 {
compatible = "intel,igc-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy";
/*
* PHY specific properties.
*/
reg = <0x0>;
};
};
};
This framework is modular and re-usable for other PCIe based Ethernet
devices. It can also be extended to support additional platform specific
information shared across child nodes.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
96 lines
2.5 KiB
C
96 lines
2.5 KiB
C
/*
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* Copyright (c) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/pcie/pcie.h>
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#include <zephyr/drivers/ethernet/eth_intel_plat.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(intel_eth_plat, CONFIG_ETHERNET_LOG_LEVEL);
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#define DT_DRV_COMPAT intel_eth_plat
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/* Device id supported in igc */
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enum i226_sku {
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INTEL_IGC_I226_LMVP = 0x5503,
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INTEL_IGC_I226_LM = 0x125B,
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INTEL_IGC_I226_V = 0x125C,
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INTEL_IGC_I226_IT = 0x125D,
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INTEL_IGC_I226_BLANK_NVM = 0x125F,
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};
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struct intel_eth_plat_cfg {
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struct pcie_dev *pcie;
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};
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struct intel_eth_plat_data {
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DEVICE_MMIO_RAM;
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mm_reg_t base;
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};
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uint32_t eth_intel_get_pcie_bdf(const struct device *dev)
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{
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const struct intel_eth_plat_cfg *cfg = dev->config;
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return cfg->pcie->bdf;
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}
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static int eth_intel_validate_sku(const struct device *dev)
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{
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const struct intel_eth_plat_cfg *cfg = dev->config;
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pcie_id_t pcie_id = cfg->pcie->id;
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switch (PCIE_ID_TO_DEV(pcie_id)) {
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case INTEL_IGC_I226_LMVP:
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case INTEL_IGC_I226_LM:
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case INTEL_IGC_I226_V:
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case INTEL_IGC_I226_IT:
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return 0;
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case INTEL_IGC_I226_BLANK_NVM:
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default:
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break;
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}
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LOG_ERR("SKU validation failed & pcie_id is %x", pcie_id);
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return -EIO;
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}
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static int intel_eth_plat_init(const struct device *dev)
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{
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const struct intel_eth_plat_cfg *cfg = dev->config;
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struct pcie_bar mbar;
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int ret;
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ret = eth_intel_validate_sku(dev);
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if (ret < 0) {
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return ret;
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}
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if (cfg->pcie->bdf == PCIE_BDF_NONE || !pcie_probe_mbar(cfg->pcie->bdf, 0, &mbar)) {
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LOG_ERR("Cannot get mbar");
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return -ENOENT;
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}
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pcie_set_cmd(cfg->pcie->bdf, PCIE_CONF_CMDSTAT_MEM | PCIE_CONF_CMDSTAT_MASTER, true);
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device_map(DEVICE_MMIO_RAM_PTR(dev), mbar.phys_addr, mbar.size, K_MEM_CACHE_NONE);
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return 0;
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}
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#define INTEL_ETH_PLAT_INIT(n) \
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DEVICE_PCIE_INST_DECLARE(n); \
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static struct intel_eth_plat_data plat_data_##n; \
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static const struct intel_eth_plat_cfg plat_cfg_##n = { \
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DEVICE_PCIE_INST_INIT(n, pcie), \
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}; \
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DEVICE_DT_INST_DEFINE(n, intel_eth_plat_init, NULL, &plat_data_##n, &plat_cfg_##n, \
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POST_KERNEL, CONFIG_PCIE_INIT_PRIORITY, NULL);
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DT_INST_FOREACH_STATUS_OKAY(INTEL_ETH_PLAT_INIT)
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