c9ce311aaa
The Xilinx AXI DMA Controller is commonly used in FPGA designs. For example, it is a part of the 1G/2.5G AXI Ethernet subsystem. This patch adds a driver for the Xilinx AXI DMA that supports single MM2S and S2MM channels as well as the control and status streams used by the AXI Ethernet subsystem. Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
29 lines
770 B
C
29 lines
770 B
C
/** @file
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* @brief Definitions and non-standard functions for Xilinx AXI DMA.
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*/
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/*
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* Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef DMA_XILINX_AXI_DMA_H
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#define DMA_XILINX_AXI_DMA_H
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#define XILINX_AXI_DMA_NUM_CHANNELS 2
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#define XILINX_AXI_DMA_TX_CHANNEL_NUM 0
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#define XILINX_AXI_DMA_RX_CHANNEL_NUM 1
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#define XILINX_AXI_DMA_LINKED_CHANNEL_NO_CSUM_OFFLOAD 0x0
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#define XILINX_AXI_DMA_LINKED_CHANNEL_FULL_CSUM_OFFLOAD 0x1
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#include <stdint.h>
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#include <zephyr/device.h>
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/**
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* @brief Returns the size of the last RX transfer conducted by the DMA, based on the descriptor
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* status.
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*/
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extern uint32_t dma_xilinx_axi_dma_last_received_frame_length(const struct device *dev);
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#endif
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