b68058787e
Previously, the CMSDK APB dual timer driver hardcoded the counter clock frequency to 24 MHz, which limits reuse across SoCs and boards with different timer clock sources. This patch replaces the hardcoded frequency with a value derived from the device tree's `clocks` phandle, using the `clock-frequency` property of the referenced clock controller node. If the property is missing, it falls back to a default 24 MHz. Signed-off-by: Lidor T <lidor@exibit-iot.com>
234 lines
6.5 KiB
C
234 lines
6.5 KiB
C
/*
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT arm_cmsdk_dtimer
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#include <limits.h>
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#include <zephyr/drivers/counter.h>
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#include <zephyr/device.h>
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#include <errno.h>
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#include <zephyr/init.h>
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#include <zephyr/irq.h>
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#include <soc.h>
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#include <zephyr/drivers/clock_control/arm_clock_control.h>
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#include <zephyr/irq.h>
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#include "dualtimer_cmsdk_apb.h"
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#define DTIMER_NODE(inst) DT_INST(inst, arm_cmsdk_dtimer)
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#define CLOCK_NODE(inst) DT_PHANDLE(DTIMER_NODE(inst), clocks)
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#define HAS_DTIMER_CLOCK(inst) DT_NODE_HAS_PROP(DTIMER_NODE(inst), clocks)
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#define HAS_CLOCK_FREQUENCY(inst) DT_NODE_HAS_PROP(CLOCK_NODE(inst), clock_frequency)
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#if HAS_DTIMER_CLOCK(inst) && HAS_CLOCK_FREQUENCY(inst)
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#define DTIMER_CMSDK_FREQ(inst) \
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DT_INST_PROP_BY_PHANDLE(inst, clocks, clock_frequency)
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#else
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#define DTIMER_CMSDK_FREQ(inst) \
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24000000U /* fallback default */
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#endif /* HAS_DTIMER_CLOCK(inst) && HAS_CLOCK_FREQUENCY(inst) */
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typedef void (*dtimer_config_func_t)(const struct device *dev);
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struct dtmr_cmsdk_apb_cfg {
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struct counter_config_info info;
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volatile struct dualtimer_cmsdk_apb *dtimer;
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dtimer_config_func_t dtimer_config_func;
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/* Dualtimer Clock control in Active State */
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const struct arm_clock_control_t dtimer_cc_as;
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/* Dualtimer Clock control in Sleep State */
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const struct arm_clock_control_t dtimer_cc_ss;
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/* Dualtimer Clock control in Deep Sleep State */
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const struct arm_clock_control_t dtimer_cc_dss;
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};
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struct dtmr_cmsdk_apb_dev_data {
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counter_top_callback_t top_callback;
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void *top_user_data;
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uint32_t load;
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};
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static int dtmr_cmsdk_apb_start(const struct device *dev)
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{
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const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config;
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struct dtmr_cmsdk_apb_dev_data *data = dev->data;
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/* Set the timer reload to count */
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cfg->dtimer->timer1load = data->load;
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/* Enable the dualtimer in 32 bit mode */
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cfg->dtimer->timer1ctrl = (DUALTIMER_CTRL_EN | DUALTIMER_CTRL_SIZE_32);
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return 0;
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}
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static int dtmr_cmsdk_apb_stop(const struct device *dev)
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{
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const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config;
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/* Disable the dualtimer */
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cfg->dtimer->timer1ctrl = 0x0;
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return 0;
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}
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static int dtmr_cmsdk_apb_get_value(const struct device *dev, uint32_t *ticks)
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{
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const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config;
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struct dtmr_cmsdk_apb_dev_data *data = dev->data;
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*ticks = data->load - cfg->dtimer->timer1value;
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return 0;
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}
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static int dtmr_cmsdk_apb_set_top_value(const struct device *dev,
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const struct counter_top_cfg *top_cfg)
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{
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const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config;
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struct dtmr_cmsdk_apb_dev_data *data = dev->data;
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data->top_callback = top_cfg->callback;
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data->top_user_data = top_cfg->user_data;
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/* Store the reload value */
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data->load = top_cfg->ticks;
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/* Set the timer to count */
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if (top_cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
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/*
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* Write to background load register will not affect
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* the current value of the counter.
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*/
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cfg->dtimer->timer1bgload = top_cfg->ticks;
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} else {
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/*
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* Write to load register will also set
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* the current value of the counter.
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*/
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cfg->dtimer->timer1load = top_cfg->ticks;
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}
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/* Enable IRQ */
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cfg->dtimer->timer1ctrl |= (DUALTIMER_CTRL_INTEN
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| DUALTIMER_CTRL_MODE);
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return 0;
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}
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static uint32_t dtmr_cmsdk_apb_get_top_value(const struct device *dev)
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{
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struct dtmr_cmsdk_apb_dev_data *data = dev->data;
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uint32_t ticks = data->load;
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return ticks;
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}
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static uint32_t dtmr_cmsdk_apb_get_pending_int(const struct device *dev)
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{
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const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config;
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return cfg->dtimer->timer1ris;
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}
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static DEVICE_API(counter, dtmr_cmsdk_apb_api) = {
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.start = dtmr_cmsdk_apb_start,
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.stop = dtmr_cmsdk_apb_stop,
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.get_value = dtmr_cmsdk_apb_get_value,
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.set_top_value = dtmr_cmsdk_apb_set_top_value,
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.get_pending_int = dtmr_cmsdk_apb_get_pending_int,
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.get_top_value = dtmr_cmsdk_apb_get_top_value,
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};
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static void dtmr_cmsdk_apb_isr(const struct device *dev)
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{
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struct dtmr_cmsdk_apb_dev_data *data = dev->data;
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const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config;
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cfg->dtimer->timer1intclr = DUALTIMER_INTCLR;
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if (data->top_callback) {
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data->top_callback(dev, data->top_user_data);
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}
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}
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static int dtmr_cmsdk_apb_init(const struct device *dev)
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{
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const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config;
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#ifdef CONFIG_CLOCK_CONTROL
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/* Enable clock for subsystem */
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const struct device *const clk = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0));
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if (!device_is_ready(clk)) {
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return -ENODEV;
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}
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#ifdef CONFIG_SOC_SERIES_BEETLE
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clock_control_on(clk, (clock_control_subsys_t) &cfg->dtimer_cc_as);
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clock_control_on(clk, (clock_control_subsys_t) &cfg->dtimer_cc_ss);
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clock_control_on(clk, (clock_control_subsys_t) &cfg->dtimer_cc_dss);
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#endif /* CONFIG_SOC_SERIES_BEETLE */
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#endif /* CONFIG_CLOCK_CONTROL */
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cfg->dtimer_config_func(dev);
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return 0;
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}
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#define DTIMER_CMSDK_REG(inst) \
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((volatile struct dualtimer_cmsdk_apb *)DT_INST_REG_ADDR(inst))
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#define DTIMER_CMSDK_INIT(inst) \
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static void dtimer_cmsdk_apb_config_##inst(const struct device *dev); \
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\
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static const struct dtmr_cmsdk_apb_cfg \
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dtmr_cmsdk_apb_cfg_##inst = { \
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.info = { \
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.max_top_value = UINT32_MAX, \
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.freq = DTIMER_CMSDK_FREQ(inst), \
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.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
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.channels = 0U, \
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}, \
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.dtimer = DTIMER_CMSDK_REG(inst), \
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.dtimer_config_func = dtimer_cmsdk_apb_config_##inst, \
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.dtimer_cc_as = {.bus = CMSDK_APB, \
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.state = SOC_ACTIVE, \
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.device = DT_INST_REG_ADDR(inst),}, \
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.dtimer_cc_ss = {.bus = CMSDK_APB, \
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.state = SOC_SLEEP, \
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.device = DT_INST_REG_ADDR(inst),}, \
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.dtimer_cc_dss = {.bus = CMSDK_APB, \
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.state = SOC_DEEPSLEEP, \
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.device = DT_INST_REG_ADDR(inst),}, \
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}; \
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\
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static struct dtmr_cmsdk_apb_dev_data \
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dtmr_cmsdk_apb_dev_data_##inst = { \
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.load = UINT_MAX, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, \
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dtmr_cmsdk_apb_init, \
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NULL, \
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&dtmr_cmsdk_apb_dev_data_##inst, \
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&dtmr_cmsdk_apb_cfg_##inst, POST_KERNEL, \
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CONFIG_COUNTER_INIT_PRIORITY, \
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&dtmr_cmsdk_apb_api); \
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\
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static void dtimer_cmsdk_apb_config_##inst(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(inst), \
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DT_INST_IRQ(inst, priority), \
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dtmr_cmsdk_apb_isr, \
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DEVICE_DT_INST_GET(inst), \
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0); \
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irq_enable(DT_INST_IRQN(inst)); \
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}
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DT_INST_FOREACH_STATUS_OKAY(DTIMER_CMSDK_INIT)
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