03d3075dc8
Add clock bindings for UART/USART (1-9) peripherals in the `stm32mp2_clock.h`. Add UART/USART clocks rate reading to the STM32MP2 clock driver. Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
/*
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* Copyright (C) 2025 Savoir-faire Linux, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_rcc.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/sys/util.h>
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static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *) sub_system;
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ARG_UNUSED(dev);
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if (!IN_RANGE(pclken->bus, STM32_CLOCK_PERIPH_MIN, STM32_CLOCK_PERIPH_MAX)) {
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/* Attempt to change a wrong periph clock bit */
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return -ENOTSUP;
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}
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sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr);
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return 0;
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}
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static int stm32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *) sub_system;
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ARG_UNUSED(dev);
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if (!IN_RANGE(pclken->bus, STM32_CLOCK_PERIPH_MIN, STM32_CLOCK_PERIPH_MAX)) {
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/* Attempt to toggle a wrong periph clock bit */
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return -ENOTSUP;
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}
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sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr);
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return 0;
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}
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static int stm32_clock_control_get_subsys_rate(const struct device *dev,
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clock_control_subsys_t sub_system, uint32_t *rate)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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ARG_UNUSED(dev);
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switch (pclken->bus) {
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case STM32_CLOCK_PERIPH_USART1:
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*rate = LL_RCC_GetUARTClockFreq(LL_RCC_USART1_CLKSOURCE);
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break;
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case STM32_CLOCK_PERIPH_USART2:
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case STM32_CLOCK_PERIPH_UART4:
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*rate = LL_RCC_GetUARTClockFreq(LL_RCC_UART24_CLKSOURCE);
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break;
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case STM32_CLOCK_PERIPH_USART3:
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case STM32_CLOCK_PERIPH_UART5:
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*rate = LL_RCC_GetUARTClockFreq(LL_RCC_USART35_CLKSOURCE);
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break;
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case STM32_CLOCK_PERIPH_USART6:
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*rate = LL_RCC_GetUARTClockFreq(LL_RCC_USART6_CLKSOURCE);
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break;
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case STM32_CLOCK_PERIPH_UART7:
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case STM32_CLOCK_PERIPH_UART8:
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*rate = LL_RCC_GetUARTClockFreq(LL_RCC_UART78_CLKSOURCE);
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break;
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case STM32_CLOCK_PERIPH_UART9:
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*rate = LL_RCC_GetUARTClockFreq(LL_RCC_UART9_CLKSOURCE);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static DEVICE_API(clock_control, stm32_clock_control_api) = {
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.on = stm32_clock_control_on,
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.off = stm32_clock_control_off,
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.get_rate = stm32_clock_control_get_subsys_rate,
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};
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static int stm32_clock_control_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 0;
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}
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/**
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* @brief RCC device, note that priority is intentionally set to 1 so
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* that the device init runs just after SOC init
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*/
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DEVICE_DT_DEFINE(DT_NODELABEL(rcc), stm32_clock_control_init, NULL, NULL, NULL, PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &stm32_clock_control_api);
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