ec01159440
Removed a redundant register write to FLASH->ACTLR Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
192 lines
6.0 KiB
C
192 lines
6.0 KiB
C
/*
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* Copyright (c) 2024 Michael Hope
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT wch_rcc
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#include <stdint.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/sys/util_macro.h>
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#include <hal_ch32fun.h>
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#define WCH_RCC_CLOCK_ID_OFFSET(id) (((id) >> 5) & 0xFF)
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#define WCH_RCC_CLOCK_ID_BIT(id) ((id) & 0x1F)
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#define WCH_RCC_SYSCLK DT_PROP(DT_NODELABEL(cpu0), clock_frequency)
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#if DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v00x_pll_clock) || \
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DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v20x_30x_pll_clock)
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#define WCH_RCC_SRC_IS_PLL 1
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#if DT_NODE_HAS_COMPAT(DT_CLOCKS_CTLR(DT_INST_CLOCKS_CTLR(0)), wch_ch32v00x_hse_clock)
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#define WCH_RCC_PLL_SRC_IS_HSE 1
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#elif DT_NODE_HAS_COMPAT(DT_CLOCKS_CTLR(DT_INST_CLOCKS_CTLR(0)), wch_ch32v00x_hsi_clock)
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#define WCH_RCC_PLL_SRC_IS_HSI 1
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#endif
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#elif DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v00x_hse_clock)
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#define WCH_RCC_SRC_IS_HSE 1
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#elif DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v00x_hsi_clock)
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#define WCH_RCC_SRC_IS_HSI 1
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#endif
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struct clock_control_wch_rcc_config {
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RCC_TypeDef *regs;
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uint8_t mul;
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};
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static int clock_control_wch_rcc_on(const struct device *dev, clock_control_subsys_t sys)
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{
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const struct clock_control_wch_rcc_config *config = dev->config;
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RCC_TypeDef *regs = config->regs;
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uint8_t id = (uintptr_t)sys;
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uint32_t reg = (uint32_t)(®s->AHBPCENR + WCH_RCC_CLOCK_ID_OFFSET(id));
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uint32_t val = sys_read32(reg);
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val |= BIT(WCH_RCC_CLOCK_ID_BIT(id));
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sys_write32(val, reg);
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return 0;
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}
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static int clock_control_wch_rcc_get_rate(const struct device *dev, clock_control_subsys_t sys,
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uint32_t *rate)
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{
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const struct clock_control_wch_rcc_config *config = dev->config;
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RCC_TypeDef *regs = config->regs;
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uint32_t cfgr0 = regs->CFGR0;
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uint32_t sysclk = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
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uint32_t ahbclk = sysclk;
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if ((cfgr0 & RCC_HPRE_3) != 0) {
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/* The range 0b1000 divides by a power of 2, where 0b1000 is /2, 0b1001 is /4, etc.
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*/
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ahbclk /= 2 << ((cfgr0 & (RCC_HPRE_0 | RCC_HPRE_1 | RCC_HPRE_2)) >> 4);
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} else {
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/* The range 0b0nnn divides by n + 1, where 0b0000 is /1, 0b001 is /2, etc. */
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ahbclk /= ((cfgr0 & (RCC_HPRE_0 | RCC_HPRE_1 | RCC_HPRE_2)) >> 4) + 1;
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}
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/* The datasheet says that AHB == APB1 == APB2, but the registers imply that APB1 and APB2
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* can be divided from the AHB clock. Assume that the clock tree diagram is correct and
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* always return AHB.
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*/
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*rate = ahbclk;
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return 0;
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}
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static void clock_control_wch_rcc_setup_flash(void)
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{
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#if defined(FLASH_ACTLR_LATENCY)
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uint32_t latency;
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#if defined(CONFIG_SOC_CH32V003)
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if (WCH_RCC_SYSCLK <= 24000000) {
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latency = FLASH_ACTLR_LATENCY_0;
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} else {
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latency = FLASH_ACTLR_LATENCY_1;
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}
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#elif defined(CONFIG_SOC_SERIES_CH32V00X)
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if (WCH_RCC_SYSCLK <= 15000000) {
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latency = FLASH_ACTLR_LATENCY_0;
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} else if (WCH_RCC_SYSCLK <= 24000000) {
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latency = FLASH_ACTLR_LATENCY_1;
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} else {
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latency = FLASH_ACTLR_LATENCY_2;
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}
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#else
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#error Unrecognised SOC family
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#endif
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FLASH->ACTLR = (FLASH->ACTLR & ~FLASH_ACTLR_LATENCY) | latency;
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#endif
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}
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static DEVICE_API(clock_control, clock_control_wch_rcc_api) = {
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.on = clock_control_wch_rcc_on,
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.get_rate = clock_control_wch_rcc_get_rate,
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};
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static int clock_control_wch_rcc_init(const struct device *dev)
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{
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const struct clock_control_wch_rcc_config *config = dev->config;
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clock_control_wch_rcc_setup_flash();
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if (IS_ENABLED(CONFIG_DT_HAS_WCH_CH32V00X_PLL_CLOCK_ENABLED) ||
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IS_ENABLED(CONFIG_DT_HAS_WCH_CH32V20X_30X_PLL_CLOCK_ENABLED)) {
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/* Disable the PLL before potentially changing the input clocks. */
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RCC->CTLR &= ~RCC_PLLON;
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}
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/* Always enable the LSI. */
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RCC->RSTSCKR |= RCC_LSION;
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while ((RCC->RSTSCKR & RCC_LSIRDY) == 0) {
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}
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if (IS_ENABLED(CONFIG_DT_HAS_WCH_CH32V00X_HSI_CLOCK_ENABLED)) {
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RCC->CTLR |= RCC_HSION;
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while ((RCC->CTLR & RCC_HSIRDY) == 0) {
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}
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}
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if (IS_ENABLED(CONFIG_DT_HAS_WCH_CH32V00X_HSE_CLOCK_ENABLED)) {
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RCC->CTLR |= RCC_HSEON;
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while ((RCC->CTLR & RCC_HSERDY) == 0) {
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}
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}
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if (IS_ENABLED(CONFIG_DT_HAS_WCH_CH32V00X_PLL_CLOCK_ENABLED)) {
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if (IS_ENABLED(WCH_RCC_PLL_SRC_IS_HSE)) {
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RCC->CFGR0 |= RCC_PLLSRC;
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} else if (IS_ENABLED(WCH_RCC_PLL_SRC_IS_HSI)) {
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RCC->CFGR0 &= ~RCC_PLLSRC;
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}
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RCC->CTLR |= RCC_PLLON;
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while ((RCC->CTLR & RCC_PLLRDY) == 0) {
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}
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}
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if (IS_ENABLED(CONFIG_DT_HAS_WCH_CH32V20X_30X_PLL_CLOCK_ENABLED)) {
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if (IS_ENABLED(WCH_RCC_PLL_SRC_IS_HSE)) {
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RCC->CFGR0 |= RCC_PLLSRC;
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} else if (IS_ENABLED(WCH_RCC_PLL_SRC_IS_HSI)) {
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RCC->CFGR0 &= ~RCC_PLLSRC;
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}
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RCC->CFGR0 |= (config->mul == 18 ? 0xF : (config->mul - 2)) << 0x12;
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RCC->CTLR |= RCC_PLLON;
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while ((RCC->CTLR & RCC_PLLRDY) == 0) {
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}
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}
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if (IS_ENABLED(WCH_RCC_SRC_IS_HSI)) {
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RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_HSI;
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} else if (IS_ENABLED(WCH_RCC_SRC_IS_HSE)) {
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RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_HSE;
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} else if (IS_ENABLED(WCH_RCC_SRC_IS_PLL)) {
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RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_PLL;
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}
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RCC->CTLR |= RCC_CSSON;
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/* Clear the interrupt flags. */
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RCC->INTR = RCC_CSSC | RCC_PLLRDYC | RCC_HSERDYC | RCC_LSIRDYC;
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/* HCLK = SYSCLK = APB1 */
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RCC->CFGR0 = (RCC->CFGR0 & ~RCC_HPRE) | RCC_HPRE_DIV1;
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return 0;
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}
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#define CLOCK_CONTROL_WCH_RCC_INIT(idx) \
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static const struct clock_control_wch_rcc_config clock_control_wch_rcc_##idx##_config = { \
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.regs = (RCC_TypeDef *)DT_INST_REG_ADDR(idx), \
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.mul = DT_PROP_OR(DT_INST_CLOCKS_CTLR(idx), mul, 1), \
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}; \
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DEVICE_DT_INST_DEFINE(idx, clock_control_wch_rcc_init, NULL, NULL, \
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&clock_control_wch_rcc_##idx##_config, PRE_KERNEL_1, \
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_wch_rcc_api);
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/* There is only ever one RCC */
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CLOCK_CONTROL_WCH_RCC_INIT(0)
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