2f0715262d
Initial support of clock control driver for RX MCU Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com> Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
99 lines
3.3 KiB
C
99 lines
3.3 KiB
C
/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_rx_cgc_pclk
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#include <string.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/kernel.h>
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#include <soc.h>
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#include <zephyr/dt-bindings/clock/rx_clock.h>
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#include <zephyr/drivers/clock_control/renesas_rx_cgc.h>
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(pclkblock), okay)
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#define MSTP_REGS_ELEM(node_id, prop, idx) \
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[DT_STRING_TOKEN_BY_IDX(node_id, prop, idx)] = \
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(volatile uint32_t *)DT_REG_ADDR_BY_IDX(node_id, idx),
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static volatile uint32_t *mstp_regs[] = {
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DT_FOREACH_PROP_ELEM(DT_NODELABEL(pclkblock), reg_names, MSTP_REGS_ELEM)};
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#else
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static volatile uint32_t *mstp_regs[] = {};
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#endif
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static int clock_control_renesas_rx_on(const struct device *dev, clock_control_subsys_t sys)
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{
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struct clock_control_rx_subsys_cfg *subsys_clk = (struct clock_control_rx_subsys_cfg *)sys;
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if (!dev || !sys) {
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return -EINVAL;
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}
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renesas_rx_register_protect_disable(RENESAS_RX_REG_PROTECT_LPC_CGC_SWR);
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WRITE_BIT(*mstp_regs[subsys_clk->mstp], subsys_clk->stop_bit, false);
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renesas_rx_register_protect_enable(RENESAS_RX_REG_PROTECT_LPC_CGC_SWR);
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return 0;
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}
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static int clock_control_renesas_rx_off(const struct device *dev, clock_control_subsys_t sys)
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{
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struct clock_control_rx_subsys_cfg *subsys_clk = (struct clock_control_rx_subsys_cfg *)sys;
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if (!dev || !sys) {
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return -EINVAL;
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}
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renesas_rx_register_protect_disable(RENESAS_RX_REG_PROTECT_LPC_CGC_SWR);
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WRITE_BIT(*mstp_regs[subsys_clk->mstp], subsys_clk->stop_bit, true);
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renesas_rx_register_protect_enable(RENESAS_RX_REG_PROTECT_LPC_CGC_SWR);
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return 0;
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}
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static int clock_control_renesas_rx_get_rate(const struct device *dev, clock_control_subsys_t sys,
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uint32_t *rate)
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{
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const struct clock_control_rx_pclk_cfg *config = dev->config;
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uint32_t clk_src_rate;
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uint32_t clk_div_val;
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int ret;
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if (!device_is_ready(dev)) {
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return -ENODEV;
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}
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ret = clock_control_get_rate(config->clock_src_dev, NULL, &clk_src_rate);
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if (ret) {
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return ret;
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}
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clk_div_val = config->clk_div;
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*rate = clk_src_rate / clk_div_val;
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return 0;
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}
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static DEVICE_API(clock_control, clock_control_renesas_rx_api) = {
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.on = clock_control_renesas_rx_on,
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.off = clock_control_renesas_rx_off,
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.get_rate = clock_control_renesas_rx_get_rate,
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};
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#define RENESAS_RX_CLOCK_SOURCE(node_id) \
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COND_CODE_1(DT_NODE_HAS_PROP(node_id, clocks), (DEVICE_DT_GET(DT_CLOCKS_CTLR(node_id))), \
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DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(node_id))))
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#define INIT_PCLK(node_id) \
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static const struct clock_control_rx_pclk_cfg clock_control_cfg_##node_id = { \
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.clock_src_dev = RENESAS_RX_CLOCK_SOURCE(node_id), \
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.clk_div = DT_INST_PROP_OR(node_id, div, 1), \
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}; \
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DEVICE_DT_INST_DEFINE(node_id, NULL, NULL, NULL, &clock_control_cfg_##node_id, \
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, \
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&clock_control_renesas_rx_api);
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DT_INST_FOREACH_STATUS_OKAY(INIT_PCLK);
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