9c4d626eb1
Add support 64-bit module-idx for m55m1x series. Signed-off-by: cyliang tw <cyliang@nuvoton.com>
213 lines
7.9 KiB
C
213 lines
7.9 KiB
C
/*
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* Copyright (c) 2023 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_numaker_scc
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/clock_control_numaker.h>
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#include <zephyr/logging/log.h>
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#include <NuMicro.h>
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LOG_MODULE_REGISTER(clock_control_numaker_scc, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
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struct numaker_scc_config {
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uint32_t clk_base;
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int hxt;
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int lxt;
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int hirc48;
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uint32_t clk_pclkdiv;
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uint32_t core_clock;
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};
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#if defined(CONFIG_SOC_SERIES_M55M1X)
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static const uint64_t numaker_clkmodidx_tab[] = {
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0x0000000000000000, 0x0000000000000400, 0x0000800000000000, 0x0001008000800000,
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0x0001008000800480, 0x0001810203FF8000, 0x0001810203FF8488, 0x0002018003800000,
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0x0002800000000000, 0x0003000000000000, 0x0003800000000000, 0x0004028283FF8000,
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0x0004028001800080, 0x0004830301FF8000, 0x0005000000000000, 0x0005800000000000,
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0x0005800000000400, 0x0005800000000800, 0x0005800000000C00, 0x0006000000000000,
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0x0006838000800000, 0x0006838000800480, 0x0007000000000000, 0x0007000000000400,
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0x0007000000000800, 0x0007000000000C00, 0x0007840000800000, 0x0007800000004000,
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0x0008000000000000, 0x0008800000000000, 0x0008800000000400, 0x0008800000000800,
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0x0008800000000C00, 0x0008800000001000, 0x0008800000001400, 0x0008800000001800,
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0x0008800000001C00, 0x0008800000002000, 0x0008800000002400, 0x0009000000000000,
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0x0009800000000000, 0x000A000000000000, 0x000A800000000000, 0x000A800000000400,
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0x000A800000000800, 0x000A800000000C00, 0x000B048383FF8000, 0x000B048383FF8488,
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0x000B850000800000, 0x000C000000000000, 0x000C858401FF8000, 0x000D000000000000,
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0x000D860481FF8000, 0x000E000000000000, 0x000E800000000000, 0x000F000000000000,
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0x000F868001800000, 0x0010000000000000, 0x0010870003800000, 0x0010870003800480,
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0x0011078503878000, 0x0011800000000000, 0x0012800000000000, 0x0013000000000000,
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0x0013800000000000, 0x0013800000000400, 0x0014080583FF8000, 0x0014888003800000,
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0x0014888003800480, 0x0015000000000000, 0x0015890603FF8000, 0x0015890603FF8488,
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0x0015890603FF8910, 0x0016000000000000, 0x0016898683FF8000, 0x0016898683FF8488,
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0x00170A0003800000, 0x00170A0003800480, 0x00170A0003800900, 0x00170A0003800D80,
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0x0017800000000000, 0x0018000000000000, 0x0018000000000400, 0x0018000000000800,
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0x0018000000000C00, 0x0019800000000000, 0x001A8B0003800000, 0x001A8B0003800480,
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0x001A8B0003800900, 0x001A8B0003800D80, 0x001B000000000000, 0x001B8B8003800000,
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0x001B8B8003800480, 0x001C0C0783878000, 0x001C0C0783878484, 0x001C0C0783878908,
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0x001C0C0783878D8C, 0x001C0C0783879210, 0x001C0C0783879694, 0x001C0C0783879B18,
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0x001C0C0783879F9C, 0x001C0C880387A000, 0x001C0C880387A484, 0x001C8D0880878000,
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0x001D0D0880878000, 0x001D800000000000, 0x001E000000000000, 0x001E8D8000800000,
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0x001E8D8000800480, 0x001F0F8000800000, 0x001F0F8000800480,
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};
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#endif
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static inline int numaker_scc_on(const struct device *dev, clock_control_subsys_t subsys)
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{
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ARG_UNUSED(dev);
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struct numaker_scc_subsys *scc_subsys = (struct numaker_scc_subsys *)subsys;
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if (scc_subsys->subsys_id == NUMAKER_SCC_SUBSYS_ID_PCC) {
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SYS_UnlockReg();
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#if defined(CONFIG_SOC_SERIES_M55M1X)
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__ASSERT_NO_MSG(scc_subsys->pcc.clk_modidx < ARRAY_SIZE(numaker_clkmodidx_tab));
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CLK_EnableModuleClock(numaker_clkmodidx_tab[scc_subsys->pcc.clk_modidx]);
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#else
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CLK_EnableModuleClock(scc_subsys->pcc.clk_modidx);
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#endif
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SYS_LockReg();
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} else {
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return -EINVAL;
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}
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return 0;
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}
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static inline int numaker_scc_off(const struct device *dev, clock_control_subsys_t subsys)
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{
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ARG_UNUSED(dev);
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struct numaker_scc_subsys *scc_subsys = (struct numaker_scc_subsys *)subsys;
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if (scc_subsys->subsys_id == NUMAKER_SCC_SUBSYS_ID_PCC) {
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SYS_UnlockReg();
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#if defined(CONFIG_SOC_SERIES_M55M1X)
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__ASSERT_NO_MSG(scc_subsys->pcc.clk_modidx < ARRAY_SIZE(numaker_clkmodidx_tab));
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CLK_DisableModuleClock(numaker_clkmodidx_tab[scc_subsys->pcc.clk_modidx]);
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#else
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CLK_DisableModuleClock(scc_subsys->pcc.clk_modidx);
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#endif
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SYS_LockReg();
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} else {
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return -EINVAL;
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}
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return 0;
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}
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static inline int numaker_scc_get_rate(const struct device *dev, clock_control_subsys_t subsys,
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uint32_t *rate)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(subsys);
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ARG_UNUSED(rate);
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return -ENOTSUP;
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}
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static inline int numaker_scc_set_rate(const struct device *dev, clock_control_subsys_t subsys,
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clock_control_subsys_rate_t rate)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(subsys);
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ARG_UNUSED(rate);
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return -ENOTSUP;
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}
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static inline int numaker_scc_configure(const struct device *dev, clock_control_subsys_t subsys,
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void *data)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(data);
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struct numaker_scc_subsys *scc_subsys = (struct numaker_scc_subsys *)subsys;
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if (scc_subsys->subsys_id == NUMAKER_SCC_SUBSYS_ID_PCC) {
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SYS_UnlockReg();
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#if defined(CONFIG_SOC_SERIES_M55M1X)
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__ASSERT_NO_MSG(scc_subsys->pcc.clk_modidx < ARRAY_SIZE(numaker_clkmodidx_tab));
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CLK_SetModuleClock(numaker_clkmodidx_tab[scc_subsys->pcc.clk_modidx],
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scc_subsys->pcc.clk_src,
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scc_subsys->pcc.clk_div);
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#else
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CLK_SetModuleClock(scc_subsys->pcc.clk_modidx, scc_subsys->pcc.clk_src,
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scc_subsys->pcc.clk_div);
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#endif
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SYS_LockReg();
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} else {
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return -EINVAL;
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}
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return 0;
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}
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/* System clock controller driver registration */
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static DEVICE_API(clock_control, numaker_scc_api) = {
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.on = numaker_scc_on,
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.off = numaker_scc_off,
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.get_rate = numaker_scc_get_rate,
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.set_rate = numaker_scc_set_rate,
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.configure = numaker_scc_configure,
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};
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/* At most one compatible with status "okay" */
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
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"Requires at most one compatible with status \"okay\"");
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#define LOG_OSC_SW(osc, sw) \
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if (sw == NUMAKER_SCC_CLKSW_ENABLE) { \
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LOG_DBG("Enable " #osc); \
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} else if (sw == NUMAKER_SCC_CLKSW_DISABLE) { \
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LOG_DBG("Disable " #osc); \
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}
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static int numaker_scc_init(const struct device *dev)
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{
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const struct numaker_scc_config *cfg = dev->config;
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LOG_DBG("CLK base: 0x%08x", cfg->clk_base);
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#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hxt)
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LOG_OSC_SW(HXT, cfg->hxt);
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#endif
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#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), lxt)
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LOG_OSC_SW(LXT, cfg->lxt);
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#endif
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#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hirc48)
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LOG_OSC_SW(HIRC48, cfg->hirc48);
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#endif
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#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), clk_pclkdiv)
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LOG_DBG("CLK_PCLKDIV: 0x%08x", cfg->clk_pclkdiv);
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#endif
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#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), core_clock)
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LOG_DBG("Core clock: %d (Hz)", cfg->core_clock);
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#endif
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/*
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* soc_reset_hook() will respect above configurations and
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* actually take charge of system clock control initialization.
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*/
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SystemCoreClockUpdate();
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LOG_DBG("SystemCoreClock: %d (Hz)", SystemCoreClock);
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return 0;
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}
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#define NUMICRO_SCC_INIT(inst) \
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static const struct numaker_scc_config numaker_scc_config_##inst = { \
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.clk_base = DT_INST_REG_ADDR(inst), \
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.hxt = DT_INST_ENUM_IDX_OR(inst, hxt, NUMAKER_SCC_CLKSW_UNTOUCHED), \
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.lxt = DT_INST_ENUM_IDX_OR(inst, lxt, NUMAKER_SCC_CLKSW_UNTOUCHED), \
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.hirc48 = DT_INST_ENUM_IDX_OR(inst, hirc48, NUMAKER_SCC_CLKSW_UNTOUCHED), \
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.clk_pclkdiv = DT_INST_PROP_OR(inst, clk_pclkdiv, 0), \
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.core_clock = DT_INST_PROP_OR(inst, core_clock, 0), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, numaker_scc_init, NULL, NULL, &numaker_scc_config_##inst, \
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PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &numaker_scc_api);
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DT_INST_FOREACH_STATUS_OKAY(NUMICRO_SCC_INIT);
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