913fddb80e
Eliminate the dependency on specific configuration options for calculating the cache line size. Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
30 lines
730 B
Plaintext
30 lines
730 B
Plaintext
# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2024 ANDES Technology Inc.
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config CACHE_ANDES
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bool "ANDES external cache driver"
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default y
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depends on SOC_FAMILY_ANDES_V5
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select CACHE_HAS_DRIVER
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help
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This option enables the CACHE driver for ANDES V5 series SOC.
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if CACHE_ANDES
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config L2C_INCLUSIVE_POLICY
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bool
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depends on DT_HAS_ANDESTECH_L2C_ENABLED
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help
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When L2 cache is inclusive of L1, CPU only needs to perform operations
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on L2 cache, instead of on both L1 and L2 caches.
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config CACHE_ANDES_INIT_PRIORITY
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int "Andes cache driver init priority"
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default 60
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help
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This option controls the priority of the cache initialization.
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Lower values indicate earlier initialization.
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endif # CACHE_ANDES
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