8442b6a83f
Move all adc driver api structs into an iterable section, this allows us to verify if an api pointer is located in compatible linker section. Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
480 lines
13 KiB
C
480 lines
13 KiB
C
/*
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* Copyright (c) 2023 SILA Embedded Solutions GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/adc.h>
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#include <zephyr/drivers/spi.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/sys/util.h>
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#define ADC_CONTEXT_USES_KERNEL_TIMER 1
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#include "adc_context.h"
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LOG_MODULE_REGISTER(max11102_17, CONFIG_ADC_LOG_LEVEL);
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struct max11102_17_config {
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struct spi_dt_spec bus;
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const struct gpio_dt_spec gpio_chsel;
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uint8_t resolution;
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uint8_t channel_count;
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};
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struct max11102_17_data {
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struct adc_context ctx;
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struct k_sem acquire_signal;
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int16_t *buffer;
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int16_t *buffer_ptr;
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uint8_t current_channel_id;
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uint8_t sequence_channel_id;
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#if CONFIG_ADC_ASYNC
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struct k_thread thread;
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K_KERNEL_STACK_MEMBER(stack, CONFIG_ADC_MAX11102_17_ACQUISITION_THREAD_STACK_SIZE);
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#endif /* CONFIG_ADC_ASYNC */
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};
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static int max11102_17_switch_channel(const struct device *dev)
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{
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const struct max11102_17_config *config = dev->config;
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struct max11102_17_data *data = dev->data;
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int result;
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uint8_t buffer_rx[1];
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const struct spi_buf rx_buf[] = {{
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.buf = buffer_rx,
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.len = ARRAY_SIZE(buffer_rx),
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}};
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const struct spi_buf_set rx = {
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.buffers = rx_buf,
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.count = ARRAY_SIZE(rx_buf),
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};
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struct spi_dt_spec bus;
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memcpy(&bus, &config->bus, sizeof(bus));
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bus.config.operation |= SPI_HOLD_ON_CS;
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result = spi_read_dt(&bus, &rx);
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if (result != 0) {
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LOG_ERR("read failed with error %i", result);
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return result;
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}
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gpio_pin_set_dt(&config->gpio_chsel, data->current_channel_id);
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result = spi_read_dt(&config->bus, &rx);
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if (result != 0) {
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LOG_ERR("read failed with error %i", result);
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return result;
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}
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return 0;
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}
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static int max11102_17_channel_setup(const struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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const struct max11102_17_config *config = dev->config;
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LOG_DBG("read from ADC channel %i", channel_cfg->channel_id);
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if (channel_cfg->reference != ADC_REF_EXTERNAL0) {
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LOG_ERR("invalid reference %i", channel_cfg->reference);
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return -EINVAL;
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}
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if (channel_cfg->gain != ADC_GAIN_1) {
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LOG_ERR("invalid gain %i", channel_cfg->gain);
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return -EINVAL;
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}
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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LOG_ERR("invalid acquisition time %i", channel_cfg->acquisition_time);
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return -EINVAL;
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}
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if (channel_cfg->differential != 0) {
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LOG_ERR("differential inputs are not supported");
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return -EINVAL;
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}
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if (channel_cfg->channel_id > config->channel_count) {
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LOG_ERR("invalid channel selection %i", channel_cfg->channel_id);
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return -EINVAL;
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}
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return 0;
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}
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static int max11102_17_validate_buffer_size(const struct adc_sequence *sequence)
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{
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size_t necessary = sizeof(int16_t);
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if (sequence->options) {
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necessary *= (1 + sequence->options->extra_samplings);
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}
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if (sequence->buffer_size < necessary) {
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return -ENOMEM;
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}
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return 0;
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}
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static int max11102_17_validate_sequence(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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const struct max11102_17_config *config = dev->config;
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struct max11102_17_data *data = dev->data;
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size_t sequence_channel_count = 0;
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const size_t channel_maximum = 8*sizeof(sequence->channels);
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if (sequence->resolution != config->resolution) {
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LOG_ERR("invalid resolution");
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return -EINVAL;
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}
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for (size_t i = 0; i < channel_maximum; ++i) {
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if ((BIT(i) & sequence->channels) == 0) {
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continue;
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}
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if (i > config->channel_count) {
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LOG_ERR("invalid channel selection");
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return -EINVAL;
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}
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sequence_channel_count++;
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data->sequence_channel_id = i;
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}
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if (sequence_channel_count == 0) {
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LOG_ERR("no channel selected");
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return -EINVAL;
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}
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if (sequence_channel_count > 1) {
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LOG_ERR("multiple channels selected");
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return -EINVAL;
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}
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if (sequence->oversampling) {
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LOG_ERR("oversampling is not supported");
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return -EINVAL;
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}
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return max11102_17_validate_buffer_size(sequence);
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
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{
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struct max11102_17_data *data = CONTAINER_OF(ctx, struct max11102_17_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->buffer_ptr;
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}
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct max11102_17_data *data = CONTAINER_OF(ctx, struct max11102_17_data, ctx);
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data->buffer_ptr = data->buffer;
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k_sem_give(&data->acquire_signal);
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}
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static int max11102_17_adc_start_read(const struct device *dev, const struct adc_sequence *sequence,
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bool wait)
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{
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int result;
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struct max11102_17_data *data = dev->data;
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result = max11102_17_validate_sequence(dev, sequence);
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if (result != 0) {
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LOG_ERR("sequence validation failed");
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return result;
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}
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data->buffer = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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if (wait) {
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result = adc_context_wait_for_completion(&data->ctx);
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}
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return result;
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}
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static int max11102_17_read_sample(const struct device *dev, int16_t *sample)
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{
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const struct max11102_17_config *config = dev->config;
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int result;
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size_t trailing_bits = 15 - config->resolution;
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uint8_t buffer_rx[2];
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const struct spi_buf rx_buf[] = {{
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.buf = buffer_rx,
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.len = ARRAY_SIZE(buffer_rx),
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}};
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const struct spi_buf_set rx = {
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.buffers = rx_buf,
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.count = ARRAY_SIZE(rx_buf),
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};
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result = spi_read_dt(&config->bus, &rx);
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if (result != 0) {
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LOG_ERR("read failed with error %i", result);
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return result;
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}
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*sample = sys_get_be16(buffer_rx);
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LOG_DBG("raw sample: 0x%04X", *sample);
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*sample = *sample >> trailing_bits;
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*sample = *sample & GENMASK(config->resolution, 0);
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LOG_DBG("sample: 0x%04X", *sample);
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return 0;
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}
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static int max11102_17_adc_perform_read(const struct device *dev)
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{
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int result;
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struct max11102_17_data *data = dev->data;
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k_sem_take(&data->acquire_signal, K_FOREVER);
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if (data->sequence_channel_id != data->current_channel_id) {
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LOG_DBG("switch channel selection");
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data->current_channel_id = data->sequence_channel_id;
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max11102_17_switch_channel(dev);
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}
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result = max11102_17_read_sample(dev, data->buffer);
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if (result != 0) {
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LOG_ERR("reading sample failed");
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adc_context_complete(&data->ctx, result);
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return result;
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}
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data->buffer++;
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adc_context_on_sampling_done(&data->ctx, dev);
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return result;
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}
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#if CONFIG_ADC_ASYNC
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static int max11102_17_adc_read_async(const struct device *dev, const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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int result;
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struct max11102_17_data *data = dev->data;
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adc_context_lock(&data->ctx, true, async);
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result = max11102_17_adc_start_read(dev, sequence, true);
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adc_context_release(&data->ctx, result);
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return result;
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}
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static int max11102_17_read(const struct device *dev, const struct adc_sequence *sequence)
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{
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int result;
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struct max11102_17_data *data = dev->data;
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adc_context_lock(&data->ctx, false, NULL);
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result = max11102_17_adc_start_read(dev, sequence, true);
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adc_context_release(&data->ctx, result);
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return result;
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}
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#else
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static int max11102_17_read(const struct device *dev, const struct adc_sequence *sequence)
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{
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int result;
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struct max11102_17_data *data = dev->data;
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adc_context_lock(&data->ctx, false, NULL);
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result = max11102_17_adc_start_read(dev, sequence, false);
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while (result == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) {
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result = max11102_17_adc_perform_read(dev);
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}
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adc_context_release(&data->ctx, result);
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return result;
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}
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#endif
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#if CONFIG_ADC_ASYNC
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static void max11102_17_acquisition_thread(void *p1, void *p2, void *p3)
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{
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ARG_UNUSED(p2);
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ARG_UNUSED(p3);
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const struct device *dev = p1;
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while (true) {
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max11102_17_adc_perform_read(dev);
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}
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}
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#endif
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static int max11102_17_init(const struct device *dev)
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{
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int result;
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const struct max11102_17_config *config = dev->config;
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struct max11102_17_data *data = dev->data;
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int16_t sample;
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adc_context_init(&data->ctx);
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k_sem_init(&data->acquire_signal, 0, 1);
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if (!spi_is_ready_dt(&config->bus)) {
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LOG_ERR("SPI device is not ready");
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return -ENODEV;
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}
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switch (config->channel_count) {
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case 1:
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if (config->gpio_chsel.port != NULL) {
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LOG_ERR("GPIO for chsel set with only one channel");
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return -EINVAL;
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}
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break;
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case 2:
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if (config->gpio_chsel.port == NULL) {
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LOG_ERR("no GPIO for chsel set with two channels");
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return -EINVAL;
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}
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result = gpio_pin_configure_dt(&config->gpio_chsel, GPIO_OUTPUT_INACTIVE);
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if (result != 0) {
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LOG_ERR("failed to initialize GPIO for chsel");
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return result;
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}
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break;
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default:
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LOG_ERR("invalid number of channels (%i)", config->channel_count);
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return -EINVAL;
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}
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data->current_channel_id = 0;
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#if CONFIG_ADC_ASYNC
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k_tid_t tid = k_thread_create(
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&data->thread, data->stack, CONFIG_ADC_MAX11102_17_ACQUISITION_THREAD_STACK_SIZE,
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max11102_17_acquisition_thread, (void *)dev, NULL, NULL,
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CONFIG_ADC_MAX11102_17_ACQUISITION_THREAD_INIT_PRIO, 0, K_NO_WAIT);
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k_thread_name_set(tid, "adc_max11102_17");
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#endif
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/* power up time is one conversion cycle */
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result = max11102_17_read_sample(dev, &sample);
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if (result != 0) {
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LOG_ERR("unable to read dummy sample for power up timing");
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return result;
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}
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adc_context_unlock_unconditionally(&data->ctx);
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return result;
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}
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static DEVICE_API(adc, api) = {
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.channel_setup = max11102_17_channel_setup,
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.read = max11102_17_read,
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.ref_internal = 0,
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#ifdef CONFIG_ADC_ASYNC
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.read_async = max11102_17_adc_read_async,
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#endif
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};
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BUILD_ASSERT(CONFIG_ADC_INIT_PRIORITY > CONFIG_SPI_INIT_PRIORITY,
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"CONFIG_ADC_INIT_PRIORITY must be higher than CONFIG_SPI_INIT_PRIORITY");
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#define ADC_MAX11102_17_INST_DEFINE(index, name, res, channels) \
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static const struct max11102_17_config config_##name##_##index = { \
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.bus = SPI_DT_SPEC_INST_GET( \
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index, \
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SPI_OP_MODE_MASTER | SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \
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.gpio_chsel = GPIO_DT_SPEC_INST_GET_OR(index, chsel_gpios, {0}), \
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.resolution = res, \
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.channel_count = channels, \
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}; \
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static struct max11102_17_data data_##name##_##index; \
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DEVICE_DT_INST_DEFINE(index, max11102_17_init, NULL, &data_##name##_##index, \
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&config_##name##_##index, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
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&api);
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#define DT_DRV_COMPAT maxim_max11102
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#define ADC_MAX11102_RESOLUTION 12
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#define ADC_MAX11102_CHANNELS 2
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DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
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ADC_MAX11102_RESOLUTION, ADC_MAX11102_CHANNELS)
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#undef DT_DRV_COMPAT
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#define DT_DRV_COMPAT maxim_max11103
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#define ADC_MAX11103_RESOLUTION 12
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#define ADC_MAX11103_CHANNELS 2
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DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
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ADC_MAX11103_RESOLUTION, ADC_MAX11103_CHANNELS)
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#undef DT_DRV_COMPAT
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#define DT_DRV_COMPAT maxim_max11105
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#define ADC_MAX11105_RESOLUTION 12
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#define ADC_MAX11105_CHANNELS 1
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DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
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ADC_MAX11105_RESOLUTION, ADC_MAX11105_CHANNELS)
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#undef DT_DRV_COMPAT
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#define DT_DRV_COMPAT maxim_max11106
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#define ADC_MAX11106_RESOLUTION 10
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#define ADC_MAX11106_CHANNELS 2
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DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
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ADC_MAX11106_RESOLUTION, ADC_MAX11106_CHANNELS)
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#undef DT_DRV_COMPAT
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#define DT_DRV_COMPAT maxim_max11110
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#define ADC_MAX11110_RESOLUTION 10
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#define ADC_MAX11110_CHANNELS 1
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DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
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ADC_MAX11110_RESOLUTION, ADC_MAX11110_CHANNELS)
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#undef DT_DRV_COMPAT
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#define DT_DRV_COMPAT maxim_max11111
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#define ADC_MAX11111_RESOLUTION 8
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#define ADC_MAX11111_CHANNELS 2
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DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
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ADC_MAX11111_RESOLUTION, ADC_MAX11111_CHANNELS)
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#undef DT_DRV_COMPAT
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#define DT_DRV_COMPAT maxim_max11115
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#define ADC_MAX11115_RESOLUTION 8
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#define ADC_MAX11115_CHANNELS 1
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DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
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ADC_MAX11115_RESOLUTION, ADC_MAX11115_CHANNELS)
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#undef DT_DRV_COMPAT
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#define DT_DRV_COMPAT maxim_max11116
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#define ADC_MAX11116_RESOLUTION 8
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#define ADC_MAX11116_CHANNELS 1
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DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
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ADC_MAX11116_RESOLUTION, ADC_MAX11116_CHANNELS)
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#undef DT_DRV_COMPAT
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#define DT_DRV_COMPAT maxim_max11117
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#define ADC_MAX11117_RESOLUTION 10
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#define ADC_MAX11117_CHANNELS 1
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DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
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ADC_MAX11117_RESOLUTION, ADC_MAX11117_CHANNELS)
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#undef DT_DRV_COMPAT
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