zephyr/dts/arm/st
Erwan Gouriou 6f55a32da8 dts: stm32h7: Fix ltdc reset lines
LTDC reset lines where off by 1. Fix it.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2025-02-06 17:48:55 +01:00
..
c0 dts: arm: st: add stm32c071 dtsi files 2024-12-20 12:37:00 +01:00
f0 dts: arm: st: change sequencer and clock source properties into string 2024-12-18 15:32:35 +01:00
f1 dts: arm: st: re-enable master can gating clock for can2 2025-01-28 14:30:36 +01:00
f2 dts: arm: st: change sequencer and clock source properties into string 2024-12-18 15:32:35 +01:00
f3 dts: arm: st: change sequencer and clock source properties into string 2024-12-18 15:32:35 +01:00
f4 dts: arm: st: re-enable master can gating clock for can2 2025-01-28 14:30:36 +01:00
f7 dts: arm: stm32 devices with quadspi is named spi node 2025-01-17 19:43:06 +01:00
g0 dts: arm: st: change sequencer and clock source properties into string 2024-12-18 15:32:35 +01:00
g4 dts: arm: st: change sequencer and clock source properties into string 2024-12-18 15:32:35 +01:00
h5 dts: arm: stm32 devices with xspi is named spi node 2025-01-17 19:43:06 +01:00
h7 dts: stm32h7: Fix ltdc reset lines 2025-02-06 17:48:55 +01:00
h7rs dts: arm: st: change sequencer and clock source properties into string 2024-12-18 15:32:35 +01:00
l0 dts: arm: st: change sequencer and clock source properties into string 2024-12-18 15:32:35 +01:00
l1 dts: arm: st: change sequencer and clock source properties into string 2024-12-18 15:32:35 +01:00
l4 dts: arm: stm32 devices with octospi is named spi node 2025-01-17 19:43:06 +01:00
l5 dts: arm: stm32 devices with octospi is named spi node 2025-01-17 19:43:06 +01:00
mp1 dts: arm: st: Refactor DTSI files to use macro 2024-10-24 17:51:42 +02:00
n6 dts: arm: st: n6: add all u(s)art instances 2025-01-28 18:14:45 +01:00
u0 dts: arm: st: u0: usb_fs_phy was erroneously placed under soc 2025-02-01 00:26:22 +01:00
u5 dts: arm: stm32 devices with octospi is named spi node 2025-01-17 19:43:06 +01:00
wb dts: arm: stm32 devices with quadspi is named spi node 2025-01-17 19:43:06 +01:00
wb0 dts: arm: st: wb0: add TRNG node 2025-01-22 08:07:40 +01:00
wba dts: arm: st: change sequencer and clock source properties into string 2024-12-18 15:32:35 +01:00
wl dts: arm: st: change sequencer and clock source properties into string 2024-12-18 15:32:35 +01:00