This commit is fixing the error on clock control for the AHB3
in the stm32_clock_control_off function.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Refactors all of the clock control drivers to use a shared driver class
initialization priority configuration,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control
drivers separately from other devices. This is similar to other driver
classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
The even lower defaults for STM32 and Arm Beetle are preserved by
SoC-family level overrides.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
When CLOCK_CONTROL_NRF_FORCE_ALT is enabled then calibration is
performed outside of the driver. In that case certain Kconfig
options where present which were dedicated for case when calibration
is performed by the driver. Side effects of those options lead to
conflicts when CLOCK_CONTROL_NRF_FORCE_ALT was enabled. Fixed
those conflicts by introducing Kconfig option which indicates
whether calibration is performed by the driver or not.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
When existing stop mode 1&2, VCO is set to range 4
and should be set back to range 1 to allow full speed
operations.
Rather than setting VCO at startup, set it inside clock
setting procedure so that it could done
in clock reset procedure when existing stop modes.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This constraint on the AHB prescaler is removed.
The ahb-prescaler is allow from 1-512.
For stm32 common and stm32U5 devices.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When the MSI clock is selected as source on the stm32wbx device,
the MSI has a range to choose the MSI input frequency.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On STM32WL, HSE clock can take 2 specific options:
-hse-tcxo
-hse-div2
Enable support for these options.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Enable PWR clock unconditionally for L4, L5 and U5
like it is done on other stm32 series
Fixes#37781
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Instead of putting object files inside libzephyr.a,
simply build a separate static library as most other
driver types are doing this already.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add clock_control driver to stm32u5 support.
For this series, now deprecated STM32 clock Kconfig symbols
are not added.
Due to a divergence in MSI clock definition, PLL1 use
instead of PLL and lack of sufficient abstraction abstraction
for these a dedicated file has been added.
This should be reshuffled:
- once a better abstraction is provided by LL API for these
- when some stm32 clock control driver rework will be done
after complete removal of Kconfig STM32 clock symbols.
Tested in MSI, HSI, PLL based HSI and PLL based MSI.
Not tested on HSE due to lack of compatible hardware.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Implement a clock control driver for Microchip MEC172x handling
configuring the 32 KHz input sources for the PLL and peripheral-32k
clock domains. MEC172x differs from MEC152x. MEC152x had one 32K source
for both PLL and peripherals. MEC172x allows the two domains to use
independent 32 KHz sources. Device tree updated to provide addresses
of hardware used by the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
the macro STM32_LSE_CLOCK is always defined and therefore systems
without lse crystals hang on startup.
Used #if instead of #ifdef.
Signed-off-by: Alexander Wachter <alexander.wachter@leica-geosystems.com>
Add a new property to the "nordic,nrf-clock" binding to allow
configuration of the HFCLKAUDIO frequency.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Fix macro used in g4 file to enable LSE clock.
Then, to avoid no-op configurations, generate an error
when MSI Hardware auto calibration is selected but LSE
clock is not enabled.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To support single core stm32wlex series, cpu2 prescaler is set
only on dual core soc variants.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds a new Kconfig option CLOCK_CONTROL_NPCX_EXTERNAL_SRC.
With this option enabled, the internal 32.768 KHz clock (LFCLK) is
generated by the on-chip Crystal Oscillator (XTOSC). Otherwise, the
LFCLK is generated by the Low-Frequency Clock Generator (LFCG).
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
__LL_RCC_CALC_HCLK1_FREQ is only available for WL and WB series,
for other series __LL_RCC_CALC_HCLK_FREQ should be used.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert the various device_get_binding() calls used to get the device
clock node to use DEVICE_DT_GET. The latter is processed at link time,
so it should be a bit more efficient.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This CL introduces six properties, clock-frequency, core-prescaler,
apb1/2/3/4-prescaler in pcc (Power and Clock Controller) node to
configure clock settings. It also removed the original Kconfig options
used for the same purpose.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Rename OSC_CLK as OFMCLK to meet npcx datasheet. The Oscillator
Frequency Multiplier Clock (OFMCLK), which is derived from
High-Frequency Clock Generator (HFCG), is the source clock of cortex-m4
core and most of NPCX hardware modules.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Switch from using internal 6pf to internal 7pf load capacitor for LFXO.
Use a default clock accuracy of 50PPM as this matches lab results.
50PPM should be sufficient for common operating temperatures of
25degC +- 15.
Signed-off-by: Johan Stridkvist <johan.stridkvist@nordicsemi.no>
STM32WL series have an extra APB3 bus with the SUBGHZSPI device on it.
Add the relevant code to enable and disable that clock, and to obtain
the actual clock rate. This is enough to run the STM32 SPI driver
against it.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
NPCX clock has some limitations about the frequency range &
synchronization between core clock & other clocks. Add build assert to
check whether NPCX clock setting correct. This also fixed soc_clock.h
to consist with datasheet.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
This commit fixes the flash latency calulation in clock_control_init
for stm32wb and stm32wl series:
For these series new_hclk_freq can't be used to set the flash latency,
because the flash clk uses a different prescaler.
Without this fix, the flash latency could be set to an inadequat value
in cases wehere the new AHB3/AHB4 prescaler is different from the
new cpu1 prescler.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds missing initialization of rcc prescalers for
stm32wb and stm32wl series when hse or hsi are selected as
system clock.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
stm32wb only has a single msi clock range, in contrast to wl, l4, l5
which have a second range that is active after exit from standby mode.
This difference must be taken account of in the driver.
This commit abstracts __LL_RCC_CALC_MSI_FREQ macro such that all series
can be supported, additionally the switch to the msirange
(LL_RCC_MSI_EnableRangeSelection) is now only executed on series
that support it.
As a result stm32wb socs can use msi as sysclock.
The same should be done for stm32l0, but this commit series limits
the scope of socs to avoid getting too bloated.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commmit restructures the clock_controller code such that the cpu2
prescler assignment later can be excluded for single core socs.
The stm32wl mcu line has variants with a single cortex-m4 core
(stm32wle5), therefore the prescaler for the second clock should
only be set for dual core socs.
This commit still checks for the complete series
(CONFIG_SOC_SERIES_STM32WLX) as the single core variants are not
yet introduced, later the condition should check for a flag like
CONFIG_SOC_STM32WL5X instead.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit fixes several occurences where a struct members is wrongly
dereferenced, which causes a compile error in case the msi clock is used
as system clock.
Only affects stm32wb and stm32wl with MSI selected as sysclock.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
In prts of the code, we use rcc node "clocks" property to testify the
use of device tree for clocks configuration.
This doesn't work in case of stm32h7 m4 targets as for those,
"upstream rcc" clock configuration, such as sysclk source selection,
is done on m7 core and hence rcc node doesn't have a "clocks"
property.
To work around this, use alternate "d1cpre" property in case of
stm32h7 targets.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Cortex-M4 stm32mp1 zephyr relies on chip Cortex-A for clock
configuration.
No change is then required for conversion to dts based clocks
configuration, but we do need to exclude use of newly deprecated
Kconfig symbols.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add new symbol CLOCK_CONTROL_STM32_HAS_DTS to exclude definition
of other CLOCK_CONTROL_STM32_* symbols when dts based configuration
is in use.
CLOCK_CONTROL_STM32_HAS_DTS is defined based on availability of
"clocks" property in rcc node.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Symbol CLOCK_STM32_HSE_CLOCK will remain in use in context of stm32
clock_control configuration using device tree, cf commit
a7989f64a3.
In preparation for next change, separate it from the others symbols
definition. Also make it non dependent from other Kconfig symbols.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This is always defined since:
755d09e149 include/drivers/clock_control: stm32: Update for STM32F1
support
So the condition has currently no effect and causes the prescaler to
always be set to /2.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Now that we have specific bindings for STM32F100 devices,
we need dedicated treatment for PLL source HSI case.
Otherwise, we end up using undefined symbol STM32_PLL_PREDIV1.
Please note that previous code compiled, it was assigning
a wrong value to prediv. This had no consequence because
prediv value is forced in Cube LL functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
