Deprecate support for configuring the MCO source and prescaler from
Kconfig configurations.
This is now done by devicetree and an MCO driver instead, which also
configures the pin to be used by the MCO peripheral.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add device driver for STM32 MCO peripheral which takes configures
the MCO clock source and prescaler, and outputs it on one of the GPIO
pins.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add clock sources PLL2CLK, PLL3CLK and EXT_HSE.
Needed to check that these clocks are enabled in MCO code.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
remove check for system clock frequency in clock_stm32_ll_h7 because of
addition of fracn (difficult to handle)
Signed-off-by: Nathan Olff <nathan@kickmaker.net>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Remove all entries that as not being used.
This also update hal to re-enable warning flags
as such as -Wno-unused-variable.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.
Replace z_arm_platform_init() with platform_reset().
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rather setting the driver default in soc, make it directly at symbol
level rather than soc and clean up redundant `select` occurrences.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Add custom clock_control API for nRF platforms that allows requesting
clocks with specified minimal required attributes (accuracy, precision,
and frequency). Provide an implementation of this API for FLL16M, HFXO,
HSFLL, and LFCLK controllers in the nRF54H20 SoC.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
When omitting the clk_src definition in a child node of a pclkblock,
it uses the source of the parent node.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Allows MSTP register addresses to be changed in the device tree
to support different configuration SoCs.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This serves two main purposes:
- change the CPU clock via devicetree nodes
- provide the APB frequency to device drivers via the clock driver
interface
Theoretically this could also support choosing between the available
clock sources, but right now we only support LPOSC0 going into PLL0,
going into AHB.
Turning the PLL back off is also not supported since the only current
use case is to set the PLL frequency, turn it on, and switch the AHB
over to it.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
Reuse the file clock_stm32g0.c for the STM32U0 and
rename it to clock_stm32g0_u0.c
because the G0 and U0 series share the same clock control.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Move all dependencies of the family config to series level,
and put a disclaimer saying not to use the family config.
Change all occurrences of the family config in code to the
MCXNX4X series config.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This includes:
1) Source containing helper functions, each
implementing a command from the clock management
protocol.
2) A clock controller driver making use of said
helper functions and implementing the clock
subsystem API.
3) A DT binding for clock protocol node.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add support for the stm32h755 which is a close relative of
the stm32h745 with additional cryptography and hashing
peripherals.
Signed-off-by: Mike Banducci <michael.banducci@sandc.com>
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Clock is disabled at startup for LP core peripherals, greatly
improving power consumption in deep sleep mode.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Device tree configuration for USB serial node and clock control
fix for proper device initialization.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
This update is to support clock API for RA8
Move the clock initialize function into clock driver
Peripheral clock now has 2 more property in clock cell for enable
and disable clock to peripheral module
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
remove litex,sys-clock-frequency from litex,clk,
because we already define that in the clock-frequency of cpu0.
This can be accessed via
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
ESP32-S2 Wi-Fi clock is not initialized properly, causing
instability when scanning or connecting to a SSID.
Fixes#74899Fixes#74417
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Setting the number of memory wait cycles must take place while the clock
is set to 32MHz or less. This patch ensure the MEMWAIT register is
changed before the clock is changed from its default value (of 8MHz).
Note that in order to set MEMWAIT to 1 the power control mode must be
set to high speed (which is why the lines of code interacting with the
OPCCR register have also been moved).
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Remove address-of operator ('&') when assigning `clock_control_xxx_init`
function pointer in `DEVICE_DT_INST_DEFINE` macro.
This change aims to maintain consistency among the drivers in
`drivers/clock_control`, ensuring that all function pointer assignments
follow the same pattern.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
There was an error in calculation of LFXO INTCAP code that prevented
obtaining desired XTAL accuracy below 50PPM. The error was fixed
the accuracy should be within expected range.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Smartbodn does not have dedicated USB clock.
For USB to work PLL needs to be turned on.
To allow for flexible configuration artificial USB clock
is added that can be operated via clock_control subsystem.
This new clock turns on PLL when USB subsystem is enabled.
PLL can also be request in DT if application requires
more speed.
PLL can be automatically turned off when USB enters suspend
state and application did not requested it.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
