Correct DT property to set correct STM32_PLL_XTPRE value.
The driver bindings defined `xtpre` instead of used `xtre`
in the `DT_PROP` macro.
That allows to use F1 PLL clock with division by 2.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
When possible, replace DT_INST(0, st_stm32xx_rcc) by equivalent
DT_NODELABEL(rcc).
Also, replace DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll),
st_stm32f1_pll_clock, okay) by equivalent
DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay).
Last, don't check about rcc node label status, which is not an
optional node.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32WL features a specific HSE clock with dedicated properties.
Add a dedicated binding and update STM32 clock control driver
header to take it into account.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add initial basic description for Cortex-M33 based
stm32u5 soc series.
This encompass description for base nodes, such as:
- cpu
- flash
- clocks
- sram
Additionally, provide description for variant stm32u575Xi.
Related to clocks nodes, added bindings for stm32u5 specific
rcc node as well as msi and pll clocks.
Header file stm32_clock_control.h was also updated to support
these new bindings.
Note that for compatibility with existing definitions, clock
node describing main pll clock, known as "PLL1", was given two
labels: "pll" and "pll1".
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Implement a clock control driver for Microchip MEC172x handling
configuring the 32 KHz input sources for the PLL and peripheral-32k
clock domains. MEC172x differs from MEC152x. MEC152x had one 32K source
for both PLL and peripherals. MEC172x allows the two domains to use
independent 32 KHz sources. Device tree updated to provide addresses
of hardware used by the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Fix definition condition for APB1 and APB2.
These were not visible until now as defaulted
in Kconfig.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In prts of the code, we use rcc node "clocks" property to testify the
use of device tree for clocks configuration.
This doesn't work in case of stm32h7 m4 targets as for those,
"upstream rcc" clock configuration, such as sysclk source selection,
is done on m7 core and hence rcc node doesn't have a "clocks"
property.
To work around this, use alternate "d1cpre" property in case of
stm32h7 targets.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following introduction of dts based driver configuration (cf #34120,
#32609 and #34701), deprecate Kconfig symbols by generating a warning
when one of these symbols is used.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add specific binding for stm32f100 pll which differs from existing
stm32f1 and stm32f105 specific pll binding.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support for STM32L0 clocks bindings.
Also, add a small tweak to SYSCLK selection to factorize some lines.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to ensure backward compatibility, use the dts config
only if nodes have prop "clocks".
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To allow transition to device tree based clock configuration on
stm32 targets, rework clock_control driver to use intermediate
STM32_ macros initially defined as the equivalent Kconfig macros
for now.
Propagate the change in all code using these macros.
The reason to introduce these new macros instead of configuring
Kconfig flags using dt kconfigfunctions is that we'll need
to be able to inform users that Kconfig flags are deprecated
once the whole family conversion is done, to encourage
out of tree users to adopt this new configuration scheme.
Note: For now STM32H7 series and code is excluded.
This is the same for some series specific code such as
PLL mul/div for L0/L1 and XTRE prescaler on F1 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Clock Pulse Generator, Module Standby Software Reset, are registers
presents in Renesas Gen3 SoC series.
MSSR is used to supply clock to the different modules, shuch as timer,
or UART, it's also possible to issue a reset the different module.
CPG registers allow to get the rate or to set some divider like for
the CAN clock.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Convert from device_get_binding to DEVICE_DT_GET. In doing this we
no longer need the label in the devicetree node so we remove that.
Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert clock_control drivers from:
DEVICE_AND_API_INIT -> DEVICE_DT_DEFINE
As part of this we also changed STM32_CLOCK_CONTROL_NAME to be based on
devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds LiteX SoC Builder clock control driver for MMCM
module. It gives ability to change frequency, phase and duty cycle
on up to 7 clock outputs.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Added configuration for approach to starting system clock source.
There are 3 options: no wait, wait untill available, wait until
stable.
Added support for those modes in clock control driver which handles
low frequency source clock.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Removed all nrf_power/USB related stuff from clock control
driver to USB driver.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This commit adds basic support for the clock controller used in
lpc11u6x MCUs.
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Updated nrf clock control driver to use onoff service for managing
multiple users.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Low frequency and high frequency clocks had separate devices
while they are actually handled by single peripheral with single
interrupt. The split was done probably because opaque subsys
argument in the API was used for other purposes and there was
no way to pass the information which clock should be controlled.
Implementation changes some time ago and subsys parameter was
no longer used. It now can be used to indicate which clock should
be controlled.
Change become necessary when nrf5340 is taken into account where
there are more clocks and current approach would lead to create
multiple devices - mess.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
By adding new SoC to Zephyr drivers has to be updated.
Commit affects:
- USB driver
- support for nRF52833 added.
- support for USB_DEVICE_REMOTE_WAKEUP in hid-mouse added.
- SPI
- IEEE 802.15.4
- CLOCK CONTROL
Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
Reimplementation of clock control driver for nrf platform. It includes
latest API changes: asynchronous starting and getting clock status.
Additionally, it implements calibration algorithm which optionally
skips calibration based on no temperature change. Internal temperature
sensor is used for that.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Header files of nrfx HALs are not supposed to be included directly
but only with their names prepended with the hal/ directory (so that
an inclusion of an nrfx HAL header clearly differs from an inclusion
of an nrfx driver header).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Extended clock configuration to allow usage of external clock
source for nrf52 series.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
move clock_control.h to drivers/clock_control.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Added option to have LFCLK synthesized from HFCLK. It is not low
power but ensures constant relation between HFCLK and LFCLK and
might be useful in certain scenarios (e.g. testing).
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This commit renames the nrf5_clock_control.h and
nrf5_clock_control.c files to nrf_clock_control.h and
nrf_clock_control.c, respectively, as they are used
in nRF9160 builds, as well.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit renames the CLOCK_CONTROL_NRF5 Kconfig symbol to
CLOCK_CONTROL_NRF. The change is required to aleviates confusion
when selecting the symbol in nRF9160 SOC definition.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
* Add usbd_dc_nrfx shim
The shim is based on the previous one usbd_dc_nrf5.
For handling the USBD hardware, tested nrfx_usbd driver from nRF SDK
was used.
Briefly tested examples:
* usb/cdc_acm
* usb/dfu (USB communication only due to flash handling issues)
* usb/hid-mouse
* bluetooth/hci_usb
Signed-off-by: Paweł Zadrożniak <pawel.zadrozniak@nordicsemi.no>
