Commit Graph

4276 Commits

Author SHA1 Message Date
Vincent Geneves
f4cccd66de dts: arm: stm32: add dts support for ADC2/3 of stm32f7
This PR enables the ADC peripheral 2 & 3 for the stm32F7 soc
series from STMicroelectronics.

Signed-off-by: Vincent Geneves <vgeneves@kalray.eu>
2022-11-18 14:53:29 +00:00
Michał Barnaś
94458f88b9 ec_host_cmd: add eSPI peripheral for the host commands
This commit adds the support for host commands being transported
by the eSPI subsystem.

Signed-off-by: Michał Barnaś <mb@semihalf.com>
2022-11-18 10:11:40 +01:00
Jason Yuan
6ff0b79d74 drivers: gpio: Add TCA6424A driver
The driver supports 24 gpio pins which are numbered sequentially from
0 to 23.

Signed-off-by: Jason Yuan <jasonyuan@google.com>
2022-11-18 10:10:11 +01:00
Chris Friedt
a0b949cc1e dts: bindings: fpga: add lattice,ice40-fpga
Add Devicetree bindings for the iCE40 series of FPGAs
from Lattice Semiconductor.

Signed-off-by: Chris Friedt <cfriedt@meta.com>
2022-11-17 09:17:44 -05:00
Henri Xavier
5de23dab59 boards/arm64: Add QEMU Virt KVM support
Zephyr already has an AArch64 QEMU Virt TCG board.
We add a KVM version of it.

Signed-off-by: Henri Xavier <datacomos@huawei.com>
2022-11-17 11:16:08 +01:00
Benjamin Perseghetti
9a491a1b5b boards: rddrone_fmuk66 dts: fxas21002 on SPI
Added support for fxas21002 sensor over SPI bus on
RDDRONE board and proper selection through dts.
Tested with fxas21002 sensor on RDDRONE.

Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Co-authored-by: Sumit Batra <sumit.batra@nxp.com>
2022-11-16 10:18:46 -06:00
Benjamin Perseghetti
a0418f9cf0 boards: rddrone_fmuk66 dts: fxos8700 on SPI
Added support for fxos8700 sensor over SPI bus on
RDDRONE board and proper selection through dts.
Tested with fxos8700 sensor on RDDRONE.

Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Co-authored-by: Sumit Batra <sumit.batra@nxp.com>
2022-11-16 10:18:46 -06:00
Mahesh Mahadevan
df42cf366e dts: nxp: Add FlexSPI2 defines for RT595
Adding FlexSPI2 for RT595

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-11-16 11:19:01 +01:00
Johan Hedberg
fb2f686c68 drivers: virtualization: ivshmem: Convert to use dynamic BDF lookup
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-16 11:18:43 +01:00
Johan Hedberg
cb1e4509fe drivers: pci: ptm: Convert to use dynamic BDF lookup
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-16 11:18:43 +01:00
Johan Hedberg
3c762f845e drivers: i2c_dw: Convert to use dynamic BDF lookup
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-16 11:18:43 +01:00
Johan Hedberg
e9b39efe9e drivers: can: kvaser_pci: Convert to use dynamic BDF lookup
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-16 11:18:43 +01:00
Johan Hedberg
c905b4dded drivers: eth_e1000: Convert to use dynamic BDF lookup
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-16 11:18:43 +01:00
Johan Hedberg
fcfff0633e drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup
Convert the ns16550 driver to use the new centralized runtime BDF lookup
of PCIe devices.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-16 11:18:43 +01:00
Johan Hedberg
0eed096f99 pcie: Add support for centralized lookup of BDF values
The BDF values can differ on the same platform, based on e.g. BIOS
configuration, and in the case of qemu the command line parameters. It's
therefore more reliable to always look up the BDF value based on the
known Vendor and Device IDs.

This patch introduces such a framework, and allows the incremental
update of PCIe drivers to start taking advantage of it.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-16 11:18:43 +01:00
Henrik Brix Andersen
1885bee7c3 drivers: eeprom: add fake EEPROM driver
Add a FFF-based fake EEPROM driver which can be used either as a stub or a
mock for testing.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-11-15 09:43:42 -06:00
Gregers Gram Rygg
f9b5138097 drivers: flash: spi_nor: add macronix high performance mode
Add property mxicy,mx25r-power-mode to jedec,spi-nor binding for
controlling low power/high performance mode on Macronix MX25R* Ultra Low
Power flash devices.

- "low-power" configures the flash in ultra low power mode.
- "high-performance" configures the flash in high performance mode.

Signed-off-by: Gregers Gram Rygg <gregers.gram.rygg@nordicsemi.no>
2022-11-15 14:58:26 +01:00
Kristofer Jonsson
1ff321baea dts: add Arm Ethos-U bindings
Updating mps3_an547 board files with DTB entries for Ethos-U.

Adding DTS bindings for the Ethos-U DTB entry.

Signed-off-by: Kristofer Jonsson <kristofer.jonsson@arm.com>
Signed-off-by: Fredrik Knutsson <fredrik.knutsson@arm.com>
2022-11-15 14:47:43 +01:00
Jędrzej Ciupis
cebf6306de dts: arm: nordic: add ieee802154 node to nrf5340_cpuapp
This commit adds an ieee802154 node to the list of nRF5340 application
core's peripherals. While it does not translate directly into a physical
RADIO peripheral, it represents the capability to use the ieee802154
radio (indirectly, through the network core).

Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
2022-11-15 12:13:46 +00:00
Yonatan Schachter
6bb93008fa dts: rp2040: Add flash controller
Add flash controller support for Raspberry Pi's RP2040 SoC

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2022-11-15 12:12:00 +00:00
Yonatan Schachter
f633b17c7c drivers: flash: Add flash driver for rpi_pico series
Add a flash driver for the rpi_pico

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2022-11-15 12:12:00 +00:00
Gerard Marull-Paretas
af722062c1 drivers: sensor: ina23x: s/irq-gpios/alert-gpios
The sensor uses the ALERT terminology (pin can be configured to trigger
on certain events such as conversion ready or overvoltage alerts). The
"IRQ" name is not clear.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-11-15 10:23:17 +01:00
Gerard Marull-Paretas
d5734bc003 drivers: sensor: ina23x: specify current LSB in uA and fix units
Specify the units of the current LSB in microamperes, so that we can
measure low maximum currents. Right now it was specified in
milliamperes, but ignored and always hardcoded to 1mA in the driver.
This makes the driver pretty much useless when the maximum current to be
measured is in a range of e.g. 20-50mA.

This patch also removes some unnecessary ifdeffery: since we write the
calibration register, we can always provice measurements with the right
units. It is also wrong to provide sensor readings that do not match
with the units specified by the channel. After this change voltage is
always reported in V, current in A and power in W.

Note that power measurement had the current LSB hardcoded in the
calculation (assuming 1mA/LSB), this has been fixed as well.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-11-15 10:23:17 +01:00
Gerard Marull-Paretas
a79f5b87c0 drivers: sensor: ina23x: s/rshunt/rshunt-milliohms
Following dtschema practices, add phyisical units to the shunt resistor
value: milliohms.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-11-15 10:23:17 +01:00
Gerard Marull-Paretas
561eb2b5b5 drivers: regulator: s/pmic/pca9420
The "pmic" driver was in reality a driver for NXP PCA9420 PMIC. There's
no "universal PMIC". While the driver may work for other NXP PMICs, it
is clearly not generic for other vendors PMIC.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-11-14 16:59:05 +01:00
Tomasz Moń
8981015335 drivers: flashdisk: support read-only flashdisks
Force cache-size to 0 and treat flashdisk as read-only when backing
partition has read-only flag set. This allows users to save RAM when the
application does not write to the flashdisk, e.g. when a predefined FAT
filesystem is used.

Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
2022-11-14 16:37:04 +01:00
Jay Vasanth
acf473f850 driver: peci: mec: enable peci in ec subsystem register
Ensure that PECI block is enabled in the EC Subsystem by clearing
the PECI_DIS (peci disable) register

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-11-10 22:39:43 -05:00
Kumar Gala
a1d0120d91 intel_adsp: Sort SoC nodes by address
Sort SoC nodes by address to make it easier to find them.  As part
of this also move the intel-sha node under SoC where it belongs.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2022-11-10 22:09:14 -05:00
Guillaume Gautier
bd5eea7a50 dts: bindings: ospi: Require STM32 OSPI clock-names binding
Following the modification of the STM32 OSPI driver, the clock-names
binding is now required

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2022-11-10 11:28:18 +00:00
Guillaume Gautier
59d6b94a40 dts: arm: st: Add clock names for all STM32 OSPI instances in dts
For all STM32 featuring octospi, clock-names are added to use them
instead of indexing for configuring the clock.
For U5 series, a third clock is added for the OSPI manager.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2022-11-10 11:28:18 +00:00
Guillaume Gautier
24680021b7 dts: bindings: clock: add bypass property to stm32 lse
For STM32 LSE clock, add LSE bypass property (defaulting to false)

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2022-11-10 11:27:49 +00:00
Armin Brauns
2d56e4b41e dts: stm32f7: fix locations of stm32-temp-cal registers
The only supported device in the F7 family with temp-cal registers at
0x1FF07A2C is the stm32f723. All other devices use 0x1FF0F44C.

part               | DS#       | TS_CAL1     | TS_CAL2
-------------------|-----------|-------------|------------
722/723            | [DS11853] | 0x1FF0 7A2C | 0x1FF0 7A2E
745/746            | [DS10916] | 0x1FF0 F44C | 0x1FF0 F44E
750                | [DS12535] | 0x1FF0 F44C | 0x1FF0 F44E
756                | [DS10915] | 0x1FF0 F44C | 0x1FF0 F44E
765/767/768/769    | [DS11532] | 0x1FF0 F44C | 0x1FF0 F44E

[DS11853]: https://www.st.com/resource/en/datasheet/stm32f722ve.pdf
[DS10916]: https://www.st.com/resource/en/datasheet/stm32f746ng.pdf
[DS12535]: https://www.st.com/resource/en/datasheet/stm32f750v8.pdf
[DS10915]: https://www.st.com/resource/en/datasheet/stm32f756ng.pdf
[DS11532]: https://www.st.com/resource/en/datasheet/stm32f765zg.pdf

Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
2022-11-09 10:48:28 -06:00
Adrian Bonislawski
728e387aa2 dts: xtensa: intel: fix alh instances
"alh0: alh1:" will create only one instance and this needs to be
reverted to original form with two instances

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2022-11-09 09:09:20 -06:00
Kumar Gala
bf5afbf823 intel_adsp: Move power domains under lps node for now
As the power domain nodes don't represent something accessible via
a MMIO register move those under the lps node to address warnings
generated when building the DTS.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2022-11-09 06:39:58 -05:00
William MARTIN
9aaeeb25d1 soc: arm: st_stm32: stm32f0: Add support for stm32f030x6
This commit adds the soc config for the STM32F030X6.

Signed-off-by: William MARTIN <william.martin@power-lan.com>
2022-11-09 10:43:41 +01:00
Hubert Miś
dc9d479dea ipc: add a multi-endpoint feature to icmsg
The icmsg backend for ipc_service has a limitation of supporting only
on endpoint. This limitation is acceptable for many IPC instances.
However, some require to use multiple endpoints sharing a single
instance. To preserve the simple and the most efficient single-instance
backend, a separated backend is introduced implementing a wrapper
around icmsg core which adds multiple endpoints support.

There are two multi-endpoint ipc_service icmsg backends: one in the
initiator role, and the other one in the follower role. In a IPC
configuration one end of communication must be in the follower role
while the other one is in the initiator. The initiator initiates
an endpoint discovery handshake to establish enpoint identifiers for
requested endpoint names. The follower responds to requests sent by
the initiator.

Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
2022-11-09 10:41:43 +01:00
Tomislav Milkovic
4088f6c40d dts: arm: st: l4: add support for STM32L486 and STM32L4A6
This families differ from STM32L476 and STM32L4A6 only in AES peripheral

Signed-off-by: Tomislav Milkovic <tomislav.milkovic95@gmail.com>
2022-11-08 10:46:16 +01:00
Tom Burdick
74b9699213 spi: SAM support SPI transfers with DMA
For larger transfers DMA can be used enabling other tasks
to continue running. A threshold of 32 byte transfers
is about right and is defined threshold value for using DMA.

This does not currently support multiple SPI transactions changing
chip select with DMA (though the hardware supports this) currently.
Instead opting for the simpler first change of enabling one shot
DMA SPI transfers for those where the size warrants it.

Adds the loopback binding option to enable the spi_loopback test.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-11-08 09:37:59 +00:00
Tom Burdick
9270f6b634 dts: same70 Disable xdmac by default
Set the status of the DMA controller, xdmac, to disabled. In effect
changing the default status from okay to disabled for all sam e70
based board.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-11-08 09:37:59 +00:00
Dat Nguyen Duy
6664953f12 drivers: gpio: support GPIO input with interrupt for NXP S32Z27
Add support input interrupts for GPIO pins on NXP S32Z27
SoC. The driver will convert GPIO pin to respective
interrupt line that will be processed by External
Interrupt Controller.

Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
2022-11-04 17:44:08 -04:00
Dat Nguyen Duy
607358b084 drivers: interrupt_controller: initial support for NXP S32Z27 EIRQ
Add initial support for the NXP S32Z27 SIUL2 External
Interrupt Controller. Each SIUL2 node has a child node
will act as an interrupt-controller that processes external
interrupt signals.

This driver is required to manage GPIO interrupts.

Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
2022-11-04 17:44:08 -04:00
Stancu Florin
42915e498e drivers: ti: cc13xx/cc26xx: implement ADC driver
New ADC driver for the TI CC13xx/CC26xx family.

ADC channel configurations are translated from Zephyr constants to
simplelink driverlib ones (e.g., sample times use a lookup table).

Async mode was also implemented & tested.

Signed-off-by: Stancu Florin <niflostancu@gmail.com>
2022-11-04 17:31:59 -04:00
Kamil Serwus
cad62fae61 soc: atmel: add base support for C2x SOC
Adds Atmel SAMC20 and SAMC21 soc. C series is based on Cortex-M0+.
C21 contains CAN interface.

The init routines are same for SAMC20 and SAMC21. They use one
clock OSC48M without configuration.

The code is inspirated from atmel_sam0/samd21.

Signed-off-by: Kamil Serwus <kserwus@gmail.com>
2022-11-04 16:03:01 +01:00
Artur Hadasz
382cba8e60 dts: bindings: nordic,nrf21540-fem: add supply voltage parameter
This commit adds an optional property to the nRF21540 Front-End Module
devicetree description that specifies supply voltage in mV. This
property can be used by the nRF21540 driver to compensate the value of
achieved gain for different supply voltage.

Signed-off-by: Artur Hadasz <artur.hadasz@nordicsemi.no>
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
2022-11-04 12:02:50 +01:00
Francois Ramu
75da6091be dts: arm: stm32mp1 family has DMA and DMAMUX instances
Define the DMA and DMAMUX peripheral for the stm32MP1
DMA1 and 2 are of type V1 of 8 streams (channels) each
with a DMAMUX peripheral. See the RefManual for details.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-11-04 10:16:56 +01:00
Peter Johanson
4b102bd7a5 dts: bindings: gpio: Add SparkFun Pro Micro header
Add SparkFun Pro Micro header connector that is implemented by many
other controllers. This allows hardware with compatible headers to
define the related GPIOs and peripherals.

Signed-off-by: Peter Johanson <peter@peterjohanson.com>
2022-11-03 18:15:38 +01:00
Peter Johanson
eb433f3051 dts: bindings: vendor-prefixes: add SparkFun
Add SparkFun (https://www.sparkfun.com/) vendor prefix.

Signed-off-by: Peter Johanson <peter@peterjohanson.com>
2022-11-03 18:15:38 +01:00
Jaska Uimonen
dd1c88d548 dts: xtensa: intel: fix alh base addr for cavs25
Cavs25 alh definition is currently the same as in ace platform, which is
wrong, thus fix it.

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2022-11-03 10:23:49 +01:00
Marcin Niestroj
adfc705b51 ARM: nxp_imx: rt10xx: migrate ARM, AHB and IPG dividers to DT
Those dividers were configured in Kconfig so far. Add 'arm-podf',
'ahb-podf' and 'ipg-podf' "fixed-factor-clock" compatible DT child nodes
under 'ccm' (Clock Control Module) and use configured 'clock-div' values
instead of Kconfig equivalents.

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-11-02 17:17:27 -05:00
Guy Morand
75ad125db8 arm: soc: nxp_lpc: Enable sctimer for LPC55S36
This is required to enable the PWM driver.

Signed-off-by: Guy Morand <guy.morand@bytesatwork.ch>
2022-11-02 16:57:50 -05:00