Commit Graph

10 Commits

Author SHA1 Message Date
Kumar Gala
5ef93aa639 tests: kernel: interrupt: Exclude platforms test isnt valid on
The test assumes that the last to IRQ numbers will be free, this isn't a
valid assumption and now that we detect multiple ISRs registering for
the some IRQ line, we see failures because of this assumption on some
platforms.  Exclude those platforms from this test for the time being.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-02-07 15:58:43 -05:00
Ioannis Glaropoulos
2782a00a00 tests: kernel: interrupt: group IRQ line number selection together
This commit moves the definition of IRQ_LINE(..) macro from
interrupt.h into nested_irq.c, and adds some inline comments
documenting the use of it.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-02-04 20:50:59 -05:00
Anas Nashif
a93651085e boards: remove pulpino board
This board is unmaintained and unsupported. It is not known to work and
has lots of conditional code across the tree that makes code
unmaintainable.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-01-31 22:47:18 -05:00
Anas Nashif
5060ca6a30 cmake: increase minimal required version to 3.13.1
Move to latest cmake version with many bug fixes and enhancements.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2019-01-03 11:51:29 -05:00
Spoorthi K
e62e54bdcd tests: interrupt: Change IRQ priorities in test
Keeping IRQ0 priority as 1 and IRQ1 priority as 0
so that system timer which of priority 0 in ARC
will be interrupted by IRQ1 of same priority.
In ARM, system timer is of priority 1, hence
making ISR0 priority as 2 and ISR1 priority as 1.
Thus system timer will always be interrupted by
ISR1 in both the architectures.

Fixes: #12147

Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
2018-12-21 21:04:36 +01:00
Spoorthi K
82f73bd5e3 tests: nested_irq: Fix k_busy_wait usage and interrupt priority
k_busy_wait() call used in test expects time in us, but the test
is specifying wait in ms.

Also the test fails on NRF5 platform as the test hardcodes the
interrupts priority to 0 and 1 and assumes system timer to be of
priority 0 which is not the case in NRF5 platforms as per
@pizi-nordic where system timer is at priority 1. Hence changing
test interrupts to 1 and 2.

Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
2018-12-11 13:36:52 -05:00
Andy Ross
ea35343eb1 tests/kernel/interrupt: Shrink very long k_busy_wait() argument
This test was written with an outrageously long timeout of 25 seconds.
That blows right through the 32 bit cycle counter on qemu_cortex_m3[1]
and produces an essentially random delay instead of the desired
number, causing a hang with the new SysTick driver in tickless mode.

Push the number down so it doesn't overflow.  The root cause, though,
is that k_busy_wait() can take arguments it can't handle.  It ought to
have an outer loop or something so that it can spin for INT_MAX
milliseconds correctly.

[1] Which has a 12MHz clock rate.  Many hardware implementations are
much faster still.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-11-13 17:10:07 -05:00
Reto Schneider
7eabab2f5d samples, tests: Use semi-accurate project names
When using an IDE (e.g. Eclipse, Qt Creator), the project name gets
displayed. This greatly simplifies the navigation between projects when
having many of them open at the same time. Naming every project "NONE"
defeats this functionality.

This patch tries to use sensible project names while not duplicating
too much of what is already represented in the path. This is done by
using the name of the directory the relevant CMakeLists.txt file is
stored in. To ensure unique project names in the samples (and again, in
the tests folder) folder, small manual adjustments have been done.

Signed-off-by: Reto Schneider <code@reto-schneider.ch>
2018-10-27 21:31:25 -04:00
Anas Nashif
d3ed3f11fa tests: interrupt: disable riscv32
This is a new test and we have riscv32 failing on that all of the
sudden. Disabling while we look into it and identify if that is a
testcase issue or not.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-16 21:27:23 -04:00
Ajay Kishore
2a103ea674 tests: add tests to validate interrupt nesting feature
This test is intended to verify the interrupt nesting.
Interrupt nesting feature allows an ISR to be preempted
in mid-execution if a higher priority interrupt is signaled.
The lower priority ISR resumes execution once the higher
priority ISR has completed its processing.

Signed-off-by: Ajay Kishore <ajay.kishore@intel.com>
2018-10-10 19:59:47 -04:00