Some drivers may not support simultaneous input-output
configuration or disconnect.
In such cases, the driver should return `-ENOTSUP` and the
test should be skipped.
Fixes#46917
Signed-off-by: Christopher Friedt <cfriedt@fb.com>
Update test suite to leverage new ZTEST APIs.
TEST=twister -T tests/drivers/watchdog/wdt_basic_api # Only build
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Updates the API and types to match updated I2C terminology. Replaces master
with controller and slave with target.
Updates all drivers to match the changed macros, types, and API signatures.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The test_adc.c still have hardcoded information on a board basis,
that need to be added manually.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
STM32_DT_CLOCKS was designed to take a device tree node label name as
argument: STM32_DT_CLOCKS(uart1)
Change its implementation to take a node identifier instead:
STM32_DT_CLOCKS(DT_NODELABEL(uart1)).
This make its usage more flexible since the argument can now be extracted
from other DT macros such as DT_PARENT. Then, the following can be done:
STM32_DT_CLOCKS(DT_PARENT(child_node_label)).
Since it is now possible implement STM32_DT_INST_CLOCKS using
STM32_DT_CLOCKS.
Finally, update existing STM32_DT_CLOCKS users and convert
STM32_INST_CLOCK_INFO users to STM32_CLOCK_INFO.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Simple driver that allows one to choose the clock speed of xtensa cores.
It's basically a shim layer on top of SOC level driver.
Also, a really simple test case was added, mainly to ensure things are
build and are sane.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Enable testcases under tests/drivers/gpio/gpio_basic_api
To run in twister, "-X gpio_loopback" parameter is needed.
Signed-off-by: Yinfang Wang <yinfang.wang@intel.com>
- The MX25UM51345G flash is connected to FLEXSPI PortA for
mimxrt595_evk.
- Updated flexspi_mx25um51345g driver to support DTR OPI mode.
- Tested with tests/drivers/flash.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
Add watchdog support to the mimxrt595 platform.
The mimxrt595 platform is excluded from the watchdog
test case because the test case uses variables in the
noinit section that need to be retained through a reset
but the rt595 does not retain this memory through a
reset.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
Enable access to the HS_SPI pins(JP26) on the mimxrt595_evk board.
Using DMA mode, tested with spi_loopback testcase.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
The reserved memory mechanism (sections and regions definition) has been
entirely replaced, greatly extended and made it better by the work done
on the zephyr,memory-region compatible.
Since there is are no actual users, we can remove it.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Move away from 'modem_pin' abstraction as it has not obvious value compared
to generic 'gpio_dt_spec'.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Move away from 'modem_pin' abstraction as it has not obvious value compared
to generic 'gpio_dt_spec'.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Move away from 'modem_pin' abstraction as it has not obvious value compared
to generic 'gpio_dt_spec'.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Move away from 'modem_pin' abstraction as it has not obvious value compared
to generic 'gpio_dt_spec'.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Enable testcases under tests/drivers/gpio/gpio_basic_api
To run in twister, "-X gpio_loopback" parameter is needed
Signed-off-by: Hu Zhenyu <zhenyu.hu@intel.com>
A test is added that uses the new device and verifies that all
desired memory is included in the core dump when a crash occurs.
Signed-off-by: Mark Holden <mholden@fb.com>
As the SPI_SLAVE define is used by some HAL (e.g. the gigadevice HAL),
SPI_SLAVE has been renamed to SPI_SLAVE_NUMBER.
Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@rtone.fr>
This PR adds support for the RT1060_EVKB as a variant of the RT1060 EVK.
Blinky app tested locally on RT1060_EVKB.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
This commit adds support for EBYTE E73-TBB.
This board features Nordic nRF52832 chip.
It was tested with several samples such as blinky and buttons.
Signed-off-by: Michal morsisko <morsisko@gmail.com>
The initialized test buffers tx_data and tx2_data were not given a
specific size, but were initialized with one more byte than the
uninitialized buffers they get copied to. As a result, the memcpy found
a buffer overflow. Fix this by setting the source buffer sizes to match
the destination.
Signed-off-by: Keith Packard <keithp@keithp.com>
This sets the dts of dma for using the uart 6 asynch api.
The stm32f746 has a dma V1 with request 5 for Tx/Rx usart6
The Tx&Rx pins (PG14, PG9) of the usart6 are connected
on the nucleo_f746zg board to pass the test
The CONFIG_DCACHE=n must also be set to disable Dcache.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This sets the dts of dma for using the uart 6 asynch api.
The stm32f767 has a dma V1 with request 5 for Tx/Rx usart6
The Tx&Rx pins (PG14, PG9) of the usart6 are connected
on the nucleo_f767zi board to pass the test
The CONFIG_DCACHE=n must also be set to disable Dcache.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Update the new API to use K_USER as the flags for both
CONFIG_USERSPACE and CONFIG_TEST_USERSPACE. Also, fix the linker
script to properly include the suites, tests, and rules.
Fixes#44108
Signed-off-by: Yuval Peress <peress@google.com>
Configure the testcase.yaml to execute watchdog testcase
wdt_basic_api on each IWDG and WWDG on all the stm32 boards
With two generic stm32 .overlay files as extra config :
one wdg is tested when the other is disabled.
Removing from board overlay.
Giving the list of boards else non-stm32 ones could try building
Signed-off-by: Francois Ramu <francois.ramu@st.com>
As now the CONFIG_NOCACHE_MEMORY is not responsible for controlling the
data cache on STM32H7 SoC, the CONFIG_DCACHE=n must be set explicitly
to preserve previous behavior as UART driver is not using no-cache
buffers.
Considering the above comment, the CONFIG_NOCACHE_MEMORY can be safely
removed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Skip the test_multiple_alarms() test when the settop value is
not supported. This is to avoid the case where wrap around
take a long time thereby causing test failures
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Instead of relying on runtime filter to limit scope to emulation
platforms, use the type attribute for each platform and do the filtering
very early on. This will speed things up for tests where we only run on
emulation platforms.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The drive-mode property is nRF specific, so prefix it with `nordic,`,
same as the `nordic,invert` property.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add support for enabling/disabling CAN-FD frame transmission/reception at
run-time.
Fixes: #45303
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Convert the can_mode enum to a bit field to prepare for future extensions
(CAN-FD mode, transmitter delay compensation, one-shot mode, 3-samples
mode, ...).
Rename the existing modes:
- CAN_NORMAL_MODE -> CAN_MODE_NORMAL
- CAN_SILENT_MODE -> CAN_MODE_LISTENONLY
- CAN_LOOPBACK_MODE -> CAN_MODE_LOOPBACK
These mode names align with the Linux naming for CAN control modes.
The old CAN_SILENT_LOOPBACK_MODE can be set with the bitmask
(CAN_MODE_LISTENONLY | CAN_MODE_LOOPBACK).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the CAN data phase API functions to timing_data_* for consistency:
- can_get_timing_min_data() -> can_get_timing_data_min()
- can_get_timing_max_data() -> can_get_timing_data_max()
- .timing_min_data -> timing_data_min
- .timing_max_data -> timing_data_max
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Since implementation of clock source selection in consumer device drivers
could be achieved without usage of a clock-names property and no
example of usage is provided up to now, remove this property from existing
examples.
Additionally, make it clear in stm32 clock control binding that it is
driver's responsibility to correctly access clock source information
and use it as required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a test section to enable device clock source selection testing.
Test targets I2C1 device which supports clock source selection
on all SOCs using this driver except L1
Initial test done on wb target.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move stm32_common tests to stm32_common_core before adding new folder
for device source selection tests.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
PLL input should be between 4 and 16MHz, so when MSI is set to 4MHz
fix PLLM can't be higher than 1.
Fix PLL1-NQR in consequence.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a stm32u5_devices test which aims at testing devices
clock control configuration on stm32u5 targets
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
