The new Nordic platforms use GRTC instead of RTC
as the system timer.
Also the nrf54h20 CPUPPR target does not have enough memory
to execute the `timer_behavior` test.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Type case CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC to uint32_t
while defining sys_clock_hw_cycles_per_sec_runtime_get()
to extend the range of frequency to 0xffffffff.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Make sure we install packages with no issues, some of the issues being
reporting on packages we might install using pip:
Warn: Project is vulnerable to: PYSEC-2019-41 / GHSA-qfc5-mcwq-26q8
Warn: Project is vulnerable to: PYSEC-2014-14 / GHSA-652x-xj99-gmcc
Warn: Project is vulnerable to: GHSA-9wx4-h78v-vm56
Warn: Project is vulnerable to: PYSEC-2014-13 / GHSA-cfj3-7x9c-4p3h
Warn: Project is vulnerable to: PYSEC-2018-28 / GHSA-x84v-xcm2-53pg
Warn: Project is vulnerable to: PYSEC-2017-74
Warn: Project is vulnerable to: GHSA-55x5-fj6c-h6m8
Warn: Project is vulnerable to: PYSEC-2014-9 / GHSA-57qw-cc2g-pv5p
Warn: Project is vulnerable to: PYSEC-2021-19 / GHSA-jq4v-f5q6-mjqq
Warn: Project is vulnerable to: GHSA-pgww-xf46-h92r
Warn: Project is vulnerable to: PYSEC-2022-230 / GHSA-wrxv-2j5q-m38w
Warn: Project is vulnerable to: PYSEC-2018-12 / GHSA-xp26-p53h-6h2p
Warn: Project is vulnerable to: PYSEC-2024-4 / GHSA-2mqj-m65w-jghx
Warn: Project is vulnerable to: PYSEC-2023-165 / GHSA-cwvm-v4w8-q58c
Warn: Project is vulnerable to: PYSEC-2022-42992 / GHSA-hcpj-qp55-gfph
Warn: Project is vulnerable to: PYSEC-2023-137 / GHSA-pr76-5cm5-w9cj
Warn: Project is vulnerable to: PYSEC-2023-161 / GHSA-wfm5-v35h-vwf4
Warn: Project is vulnerable to: GHSA-3f63-hfp8-52jq
Warn: Project is vulnerable to: GHSA-44wm-f244-xhp3
Warn: Project is vulnerable to: GHSA-56pw-mpj4-fxww
Warn: Project is vulnerable to: GHSA-j7hp-h8jx-5ppr
Warn: Project is vulnerable to: PYSEC-2023-175
Warn: Project is vulnerable to: PYSEC-2018-34 / GHSA-2fc2-6r4j-p65h
Warn: Project is vulnerable to: PYSEC-2021-856 / GHSA-5545-2q6w-2gh6
Warn: Project is vulnerable to: PYSEC-2019-108 / GHSA-9fq2-x9r6-wfmf
Warn: Project is vulnerable to: PYSEC-2018-33 / GHSA-cw6w-4rcx-xphc
Warn: Project is vulnerable to: PYSEC-2021-857 / GHSA-f7c7-j99h-c22f
Warn: Project is vulnerable to: GHSA-fpfv-jqm9-f5jm
Warn: Project is vulnerable to: PYSEC-2017-1 / GHSA-frgw-fgh6-9g52
Warn: Project is vulnerable to: GHSA-c6fm-rgw4-8q73
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Test test_one_tick_timer_train was failing due not being able to
execute enough 1 tick timeouts. Decrease system ticks frequency
to make the test pass.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Adjust testcase.yaml files to changes in Twister schema which
now allows multiple recording patterns ('record: regex:').
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Currently the timer_behavior test uses fabs.
Since the C library functions being used in the kernel
is restricted in Rule A.4 in the Coding Standard
We should probably not use these functions in tests either.
Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
Test test_one_tick_timer_train was failing due not being able to
execute enough 1 tick timeouts. Decrease system ticks frequency
to make the test pass.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Adjust default number of test samples which is based on SRAM size.
Test is using 8*TIMER_TEST_SAMPLES and with previous defaults for
the device with 64k RAM it was using 56k of test data leaving only
8k RAM and that was easily not enough. Adjust conditions to
take less samples when SRAM_SIZE is equal to the threshold.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
sqrtf() is used for floats but the argument and resulting
variable are both doubles. LLVM would complain about
implicit conversion from float to double. So use sqrt()
instead as it is used with doubles.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Like in C test. If MAX STDDEV is lower than single clock cycle then
set it to a single clock cycle.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
If frequency of the system clock is lower then deviation may exceed
default value (10us). Instead of adjusting the default value, test is
rounding up expected standard deviation to a single clock cycle.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
`checkpatch.pl` requires that dts sources are indented with tabs,
fix all the spaces that slipped in while checkpatch wasn't watching.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Fix incomplete test log capture when the external tool is used
and Twister Pytest Harness script ends without reading output
from the last test case running on the device.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Additional logging of kernel.timer.timer_behavior_external test case
statistics for timer drift, variance, etc. as JSON-formatted records
to make easier data collection and its further analysis.
These log records will be processed by the Twister Harness recording
feature which captures and parses timer statistics from the log output,
then composes it into twister.json and recording.csv files.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Additional logging of kernel.timer.timer test case statistics for
timer drift, variance, etc. as JSON-formatted records to make easier
data collection and its further analysis.
These log records will be processed by the Twister Harness recording
feature which captures and parses timer statistics from the log output,
then composes it into twister.json and recording.csv files.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Align grpcio version with logic2-automation package fixing its fail
on Channel.unary_unary() call with missing _registered_method argument..
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
There might be a deviation of 30.5 microseconds (1 cycle) due to the
calculation deviation between free run and event timers. This commit
increases stdev to 33 for ite platform.
Fix#67833
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Change the stdev tolerance stdev from 10 to 33 when npcx timer is used.
This is because the clock source of npcx event timer, which is used to
generate the timeout interrupt, is running at 32.768 KHz.
(i.e. 1 count = ~30.5 us.) The conversion from the absolute system timer
to the event timer count might have -30.5 ~ 30.5 deviation.
The tolerance setting is under the assumption that test sampes are
evenly located at 1030.5 and 969.5 for the worst case.
Fixes#59594
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This is a follow-up to commit 4cc21e2f4a.
That short sleeping before starting the test was removed together with
accuracy improvements (specifically, with moving of the first readout
of the cycle counter). Nevertheless, this tick alignment it still
needed, as without it in specific conditions the test may undesirably
fail.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This patch shows an example of how to use the timer behavior external
tool testing, using the Saleae Logic 2 application.
Also, some board overlays were added as examples.
Finally, testcase.yaml updated with parameters for the Saleae sample.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
This patch adds a way to simplify using an external tool to measure
timer behaviour on Zephyr. It modifies the timer behaviour
jitter_drift.c tests to toggle a GPIO pin (defined via a new DTS
compatible, "test-kernel-timer-behavior-external") that can be connected
to an external tool, such as a logic analyzer, to measure timer
behaviour.
This GPIO pin toggle is behind a new CONFIG_TIMER_EXTERNAL_TEST Kconfig.
A new pytest test is added so that it can collect the statistics from
the external tool and assert some measurements. To collect statistics
from the external tool, one needs to provide a Python module which
provides a `run(seconds, config)` method, that will perform the test and
return the statistics. Check the README file for more information about
this interface.
Finally, this on twister, this new test is behind a new fixture,
"gpio-timerout".
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Commit a1d21ca69b ("tests: timer_behavior: don't fail the test with
timer wrap-arounds") simply ignored the total time validation whenever
any rollover was detected. Let's adjust the end timestamp according
to the number of rollovers instead.
Documentation for sys_clock_cycle_get_32() says it should count up
monotonically through the full 32 bit space, wrapping at 0xffffffff.
Therefore we just need to add 2^32 times the number of rollovers to
the end timestamp.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Use 13% instead of the default 10% when the nRF RTC timer is used
so that the allowed drift is at least one tick long (~122 us in
this case).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Twister now supports using YAML lists for all fields that were written
as space-separated lists. Used twister_to_list.py script. Some artifacts
on string length are due to how ruamel dumps content.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
If the timer driver only implements sys_clock_cycle_get_32() (meaning
CONFIG_TIMER_HAS_64BIT_CYCLE_COUNTER=n) and the hardware clock is high
enough then the reported cycle count may wrap an uint32_t during the
test. This makes validating the total test duration pointless as it
cannot be measured. Just print a warning instead of failing the test
in that case.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Nordic targets use 24-bit RTC peripheral for system clock. Nordic system
clock timeout implementation relies on RTC CC (capture compare) when
the timeout is in future. Nordic system clock driver allows setting
alarm only to 3 or more counts from current counter value due to silicon
limitation (to ensure that CC event triggers before counter overflow).
RTC CC limitation does not have much impact on normal applications where
there is no need to schedule such short timeouts, but is problematic in
a timer test that expects being able to repeatedly schedule timeouts on
subsequent ticks.
Reduce system tick rate to 8192 on nRF targets to allow setting CC to
the very next tick. With system tick rate being 4 times less than the
hardware tick rate, it is always possible to schedule timeout to happen
in the next tick because ticks are 4 counts apart, i.e. current timer
value + 3 never runs past the next tick.
Fixes: #54211
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Don't sample the first entry outside the timer as this is a different
code path which produces a different offset from the clock tick.
Use sys_clock_hw_cycles_per_sec() to be compatible with systems that
read their hardware clock frequency at run time.
Perform cycle difference computations with uint64_t. If ever the
magnitude of the absolute clock cycle values is greater than 52 bits
then the cast to a double will actually lose accuracy.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
An assertion statement was a bit too strict. Period drift may come about
not only from kernel ticks being large but also from time conversion being
inexact due to division truncation.
Fixes: #55136
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Provide an estimate of the test duration.
Make the output nicer than a few overloaded and wrapped lines.
Provide more context in the presence of period time drift.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Print the "perfect" reference period for easier evaluation.
Suggest a remedy to the missed ticks problem.
Still, that wasn't satisfactory. Implemented a count of missed ticks
to get to the bottom of this issue. Found that missed ticks always came
to a perfect count of 40.
Incidentally, the busy loop prints a line every 250 ms and the test spans
10 seconds. There are no such coincidences.
Turns out that CONFIG_PRINTK_SYNC was set by default. This disables IRQs
for the serial output duration, which can be quite long at 115200 bauds.
Given a 60-ish character line length, this represents more than 5 ms of
no IRQ servicing during a timer latency measurement test which is bad.
So make sure CONFIG_PRINTK_SYNC=n for proper statistics.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Fix all line-length errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(line-length)'
Using a limit is set to 100 columns, not touching the commandlines in
GitHub workflows (at least for now).
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The requirement of being able to spend only 10% of processing time
on execution of timer handlers that are scheduled on every tick is
not really possible to fulfill on platforms like the nRF ones where
the tick period is quite short (~30 us in this case). Relax this
requirement and accept if at least one-third of the processing time
is available for other work while handling the timer tick train.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Test timers with a train of one tick timers to test that
a configured SYS_CLOCK_TICKS_PER_SEC is sensible. If the TICKS_PER_SEC
is too high the timer train will take longer than expected to reach
the station. Worse, if the timer driver has too short of a minimum
delay for its processing power and the tick rate is too high its
possible the device will get caught in an interrupt loop
preventing any threads from running while processing timers.
This test validates that the tick rate configured is actually able to be
processed without delays while also having work done in threads ensuring
that no thread scheduling delays occur either from delayed timers or an
interrupt loop from preventing threads from running.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Adds a custom test_main and renames the test suite for jitter_drift.
Runs the jitter_drift test suite.
The order of these tests matter on hardware as the counter is often
reset on loading the test program. This is useful as its far less likely
to encounter a clock counter rollover. On arm this is especially useful.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
