Added empty fp register structs for ARM combinations not handled,
i.e. any ARM without a fpu.
Signed-off-by: Lars-Ove Karlsson <lars-ove.karlsson@iar.com>
- Remove raising compilation error in `float_regs_arm_gcc.h`
These macros are checked in 'load_store.c', so no need to check them
again in 'float_regs_arm_gcc.h'
- Enable this test on the VFP platform of aarch32
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
This adds FPU sharing support with a lazy context switching algorithm.
Every thread is allowed to use FPU/SIMD registers. In fact, the compiler
may insert FPU reg accesses in anycontext to optimize even non-FP code
unless the -mgeneral-regs-only compiler flag is used, but Zephyr
currently doesn't support such a build.
It is therefore possible to do FP access in IRS as well with this patch
although IRQs are then disabled to prevent nested IRQs in such cases.
Because the thread object grows in size, some tests have to be adjusted.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
* Rename CPU_ARCV2 to ISA_ARCV2. That helps to avoid conflict between
CPU families naming and ISAs naming and aligns this options
with other ARC OSS projects.
* Generalize ARCV2 check to ARC check where it is required.
NOTE: we add ISA_ARCV2 option in a choice list as a preparation
for ISA_ARCV3 addition.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
This commit renames the `kernel.fp_sharing` tests to
`kernel.fpu_sharing`, in order to align with the recent
`CONFIG_FP_SHARING` to `CONFIG_FPU_SHARING` renaming.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
