Add qemu_riscv32, qemu_riscv32e, and qemu_riscv64 targets
to the tests that list below. These set CONFIG_MULTITHREADING=n.
- tests/kernel/fatal/no-multithreading
- tests/kernel/mem_heap/mheap_api_concept
- tests/kernel/mem_slab/mslab_api
- tests/kernel/threads/no-multithreading
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Twister now supports using YAML lists for all fields that were written
as space-separated lists. Used twister_to_list.py script. Some artifacts
on string length are due to how ruamel dumps content.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
integration_platforms help us control what get built/executed in CI and
for each PR submitted. They do not filter out platforms, instead they
just minimize the amount of builds/testing for a particular
tests/sample.
Tests still run on all supported platforms when not in integration mode.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Extended test to validate following functionality:
- k_busy_wait
- k_timer
- irq_lock/irq_unlock
- k_cpu_idle
- SYS_INIT()
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
bat_commit is an old and obsolete tag that has not been maintained over
time and was supposed to serve a purpose that is obsolete now. Also
rename core tag with kernel.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is a feature Ben added so you could use Zephyr's arch layer to
bootstrap things like bootloaders without sucking in the whole kernel.
And it's worked until now.
But we never had a test for it, and I just broke it with the scheduler
rework. Add a trivial test just to make sure this continues to link
and run. Longer term it would be nice to have some kind of size
metric here to guarantee that the feature stays lean and doesn't pull
in needless code.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
