k_cycle_get_32() needs to return a monotonically increasing value,
except in cases of 32-bit integer overflow. Enforce this with a
test case.
We also check that the number of cycles elapsed after sleeping for 1
second is at the expected value. This can help catch errors on platforms
that use different timer sources for the system clock and timestamps.
This test case adapted from some code provided by Sergey Arkhipov
when troubleshooting ZEP-1546.
Issue: ZEP-1546
Change-Id: If27fff026ea6de659f7b41b60ff26f4962b734d4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Some files made it through review process with full license header.
Change-Id: I2722b127c40b4b19500042c12e4fde85a165bae9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Timeouts, when expiring on the same tick, should be handled in the same
order they were queued.
Change-Id: I23a8e971a47ca056b32b8b48fe179d481bae27c0
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
So far, only implemented on ARM.
It's not possible to do this on Nios II and RISC-V.
Change-Id: I84c8d99cd163dff46de4bc4a7ae40768daf8e4ce
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
obj_tracing test from legacy modified to use unified APIs
directly.
Jira: ZEP-932
Change-Id: Ib5d300334e527b842668be076c94c40b65d7cbe4
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Remove tests that assert due to invocation from ISR which is not supported.
Change-Id: Ib2313b8f75db0140aa475281bd76ba0414d6a481
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
This was reported by ISSM compiler.
Jira: ZEP-1179
Change-Id: I5700ff6b374815325fa858cfd11f8938c82d8337
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
This option is added in order to support Xtensa, which needs more stack than
other architecture. This allows having a centralized way to change stack
requirements for all tests.
This extra stack size is eaqual to 0 for most architectures, except Xtensa
which requires additional 768 bytes for each stack.
Change-Id: Ie5dcae1dfd29018d36ef35dae22dc4c1a2ecdc14
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
Remove tests that assert due to invocation from ISR which is not supported.
Change-Id: Idd2360847a467af6afdd9fbed8f87a620d9ed2f7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This test is intended to verify that the SW ISR and vector tables
have been populated correctly.
Change-Id: Ic7f50c02dc0807d7ddefa710da67f818ff707ad6
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This replaces the hard-coded vector table, as well as the
software ISR table created by the linker. Now both are generated
in build via script.
Issue: ZEP-1038, ZEP-1165
Change-Id: Ie6faaf8f7ea3a7a25ecb542f6cf7740836ad7da3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These were reported by ISSM compiler.
Jira: ZEP-1179
Change-Id: Ic625749309773611c0c6ba2905e9420e98947dae
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
this commit check the priority of 2 system threads - main and idle
Change-Id: Ie57e7fdab3d15c0b69d85ed6282bfa6aa04133b4
Signed-off-by: jing wang <jing.j.wang@intel.com>
riscv defines the machine-mode timer registers that are implemented
by the all riscv SOCs that follow the riscv privileged architecture
specification.
The timer registers implemented in riscv-qemu follow this specification.
To account for future riscv SOCs, reimplement the riscv_qemu_driver by
the riscv_machine_driver.
Change-Id: I645b03c91b4e07d0f2609908decc27ba9b8240d4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
This tests access to standard libraries. Adapted
to use ZTEST.
Jira: ZEP-932
Change-Id: I3564bfa61221b2456323c1018402237b6129b5ca
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is the microkernel version of the FPU sharing test from legacy
modified to use unified APIs directly.
Jira: ZEP-932
Change-Id: I133a1466ea75201a97c2f8b83c3586fea0a19447
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This test was not using any legacy APIs, so simply
removed legacy from conf and ini's.
Jira: ZEP-932
Change-Id: I5a4b475ac5056b6d6aa64baef6bda53f20d8548e
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
The for loop could exit with a out of bounds (variable j) value for
the delayed_threads array, we verify for the variable value before
operating on the array
This issue was reported by Coverity
Coverity-CID: 160078
Change-Id: I6aa1cc325cc363be48cd72b2a58d0a55ec3854bc
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
In RISCV, stack always grows by a multiple of 16 bytes, even if we are saving
data of size < 16 bytes onto the stack.
Hence, for riscv32 architecture increase stack size to 512 for
threads_customdata, otherwise we experience stack overflow.
Change-Id: I805bc346b8a2c2f4ad6d0db622eb262290af942b
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
In RISCV, stack always grows by a multiple of 16 bytes, even if we are saving
data of size < 16 bytes onto the stack.
Hence, for riscv32 architecture a bigger stack size is required for
test_mpool_concept, otherwise we experience stack overflow.
Change-Id: I938aa511efcae66f0131fa1bc23bd68600421885
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
When trying to build with newlib we get:
hci_driver.c: In function 'hci_driver_open':
hci_driver.c:389:10:
error: format '%d' expects argument of type 'int', but argument 2 has
type 'uint32_t {aka long unsigned int}' [-Werror=format=]
BT_ERR("Required RAM size: %d, supplied: %u.", err,
^
This is because we have different types for {u}int32_t between newlib
and mini-libc. We have to decide how we are going to handle this going
forward. Various options include use of PRIu32, making mini-libc match
newlib's types, disabling the -Werror=format, etc.
Change-Id: I5df8fa05dd7658e1f6b2eeb8fa84e3270f3dd208
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
"struct k_mbox_msg mmsg" should be initialized before using.
"int" value returned by k_mem_pool_alloc() should be checked.
Coverity-CID: 160083
Coverity-CID: 160470
Change-Id: I35714bf9d76723c5fdd8c2963bf76b42ae1b1867
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
assert should not contain "i++" which might work differently in a non-debug
build.
Coverity-CID: 160469
Change-Id: Id8fd50127dd93de1676b812ac0888c9ec2e1b5de
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
"int" value returned by k_mem_pool_alloc() should be checked.
Coverity-CID: 160471
Change-Id: I7ec19147e7a51997fed890075b06eba30bef9126
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
"ret" returned from k_msgq_put() should be checked.
Coverity-CID: 160084
Change-Id: I192db3a67ab9489e8338f6636d4c2a6935e98d74
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
Convert testcases to use the CMSIS NVIC APIs or direct NVIC register
access rather than the internal ones so we can remove them in the future.
Change-Id: I2a5a3eae713e66944cf105e7fffa603b88522681
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
_NvicSwInterruptTrigger is only utilized by a testcase for irq handling
on ARM-V7M. Just put the code into the testcase so we dont need to
support an additional interface.
Change-Id: I763c63c32a7a52918250458351d08b8fa54069dd
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Some new tests were added that had the Apache 2.0 boilerplate licensing
instead of the SPDX licensing tag.
Change-Id: I4bde8c9c6e7a6d44bceeffb6bbcff9f62d417648
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
