Add a driver for the NXP MCUX Quadrature Decoder. The driver
is simple and only implements the phase a and phase b inputs. The
module has additional features which can be added in future PRs.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Change the name of the custom macro defined for the stm32 devices
to fit the VND_PWM_xxx model
Keeping old deprecated macro, though.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduce Ethernet low-level driver for NXP S32 Network Controller
(NETC). Current driver allows to manage from Zephyr a Physical Station
Interface (SI) and/or a Virtual SI. The NETC has an integrated Ethernet
Switch. Currently the Switch is initialized from this driver with a
default configuration, and all ports are enabled and transparent for
the user. A separate Switch driver should be addressed in future patches.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Introduce NXP S32 NETC External MDIO controller driver. Driver supports
a single instance, as current support is based on NXP S32Z/E SoCs.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Advertise Gigabit Ethernet if the PHY supports it. As with the
other speeds, it is assumed the PHY supports both duplex modes.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Introduce NXP S32 Message Receive Unit (MRU) driver based
of Mbox API. The MRU couples with a processor and allows to
receive messages from senders, which are other modules or
processors.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This change enables the ISR Hard Reset sent bits, so that
an interrupt is generated when a Hard Reset is sent or
the Hard Reset failed.
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
The Hard Reset sent signal was tested twice in the same
"if else" structure but only handled in the last test. This
change removes the first detection so that Hard Reset can
be correctly detected.
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
Only run the `PM_DEVICE_ACTION_TURN_ON` and `PM_DEVICE_ACTION_TURN_OFF`
actions for child devices that have refered to the domain via the
`power-domain` property.
This prevents multiple actions being run for devices that refer to
several power domains, e.g.
```
test_dev: test_dev {
compatible = "test-device-pm";
status = "okay";
power-domain = <&test_reg_1>;
alternate-domain = <&test_reg_chained>;
};
```
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The struct sensor_value type does NOT require val2 to be positive. The
removed code is in fact a rather serious bug, probably put in place
because it makes printing sensor_values easier.
Signed-off-by: Benjamin Lindqvist <benjamin@eub.se>
It's not necessary to busy wait 150 µs after changing register banks.
Nothing in the data sheet nor app note suggests this. ST's own HAL,
which is used by this driver, does not delay when changing banks. It
does a bank change around every function that accesses a non-user bank
register (it's quite inefficient).
So if it was necessary it would be broken now, as most of the bank
changes have no delay.
One of the few page changes that did have this delay are the those done
before and after reading a sensor sample. Which is where the speed is
significant and is limiting the update rate the driver is capable of.
Signed-off-by: Trent Piepho <trent.piepho@igorinstitute.com>
The code in the ST HAL does a read/modify/write to change the bits in
the LSM6DSO_FUNC_CFG_ACCESS register that control which register bank is
active.
All the other bits in the register are defined as zero. It's possible
to simply set the register to the desired value without reading the
contents first.
This bank switch needs to be done twice for every sensor read when the
sensor hub is used. The driver as it is can not keep up with the higher
update rates of the lsm6dso. So any speed increase in this code allows
for a higher update rate as well as reduced latency.
Previously, a read of the lsm6dso's accel and gyro on a 400 kHz I2C bus
with a 3-axis magnetometer on the sensor hub takes 2.69 ms. This drops
that to 2.26 ms. This is enough to support the 417 Hz ODR.
Signed-off-by: Trent Piepho <trent.piepho@igorinstitute.com>
There is a flaw with I2C communication to peripherals behind the shub
that causes sporadic failures. Especially calls to configure a device
after the lsm6dso initialization is finished, e.g. to set the ODR, can
fail to work correctly.
Access to shub peripheral registers is done by putting the parameters of
the operation into SLV0 and then waiting for the lsm6dso to perform the
xfer on the shub I2C bus. The lsm6dso does this in sync with the
accelerometer update rate. Once the shub is enabled, it peforms the
xfer repeatedly as the accelermeter is sampled.
The wait has a problem: It might detect that a previous shub xfer has
finished, which was done before SLV0 was programmed with new parameters.
The shub status register is read-to-clear. This isn't in the data sheet
or app note, but it is. By reading the status before enabling the
sensor and after programming SLV0, we can be sure when it becomes set it
has finished the current operation and not a previous one.
Also set the write-once flag before shub init. This causes the shub to
only perform I2C writes once instead of continuously. This was set at
the end of init, so any writes done during it would repeat until the
shub was disabled.
Put a timeout in the code that polls for the sensor hub op complete. It
could possibly poll forever. More importantly, if there is no device
connected to the sensor hub, the lsm6dso does not timeout on the
operation for ~13 seconds. Since the shub init does a probe for devices
on startup, this will happen if shub support is enabled but a lsm6dso
has no sensor hub devices. There could be multiple devices, some with
additional sensors and some without. Initialization of the devices
without additional sensors takes tens of seconds without this timeout
being added.
Add a 300 µs wait after disabling the sensor hub. This is necessary
according to the ST app note AN5192 §7.2.1.
Read the shub status from the main bank register instead of the shub
bank register. This avoids an extra bank switch before and after each
status poll. Actually two bank switches on each side, since the lsm6dso
driver switched banks and then the ST HAL function to get the status
register switches again.
The wait for the shub I2C transaction to finish is not needed when the
shub is enabled at the end of init. We aren't starting a new I2C write
or reading the result of a read.
Signed-off-by: Trent Piepho <trent.piepho@igorinstitute.com>
The lsm6dso initialization will fail if the device is not already set to
the user register bank. All the registers used will be the wrong ones
from whatever bank it is in, e.g. sensor hub bank. This includes the
registers to reset the device!
The bank will default to the user bank on reset, but the chip has no
hardware reset line. On a reboot it will be in whatever bank it was
last in. If the sensor hub is enabled, it will switch banks on every
sample, so it's entirely possible to reset or reboot when it happens
to be set to the sensor hub bank, which will cause the driver to
fail to initialize. It will not work again until the lsm6dso is power
cycled.
Signed-off-by: Trent Piepho <trent.piepho@igorinstitute.com>
Per an ST app note, the sensor hub I2C controller should be disabled
before doing a software reset. Possibly, this is because the sensor hub
could be in the middle of the an I2C transaction to a sensor when it is
reset. Disabling it and then waiting makes sure it has quiesced before
resetting.
Signed-off-by: Trent Piepho <trent.piepho@igorinstitute.com>
The initialization code would configure the lsm6dso interrupt, then
configure the rest of the chip. The chip init includes a reset that
would undo the register setting done during interrupt configuration.
It's also not a good idea to enable the interrupt on the SoC when the
lsm6dso has not yet been reset or configured. It might be generating
interrupts.
The lsm6dso has no hardware reset line, so it will not be reset on
reboot unless a power cycle is involved.
Signed-off-by: Trent Piepho <trent.piepho@igorinstitute.com>
The DMA API contract specifies that start/stop may be called multiple
times. Prior to adding power management this was perfectly fine as it was.
In adding power management, there are additional side effects that can
cause issues. Instead check the state of the channel prior to start/stop
and do nothing if already in the desired state.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
When transceiver is overload on reception a frame can be stored on
the internal buffer without processing a frame start interrupt. The
frame will complete and system will received a interrupt and signal
receiver thread with an isr_status equal to 0x2c.
The current implementation process one flag at time and it may hang
when status is 0x2c. This issue can be reproduced using two nodes
where one perform a regular TX broadcast and tThe other one should
be wait for frames. The receptor should run on debug mode and system
should be started normally. The problem happens when pressing CTRL+C
on the debugger, which will cause system to stop. However, the
transceiver still can receive one last frame. After a few transmission
user can continue application and a isr_status of 0x2c will be visible
if CONFIG_IEEE802154_DRIVER_LOG_DEBUG is enabled.
This fixes the current issue by processing all RF2XX_TRX_END events.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
A call to exit_dpd mode for the nrf QSPI nor flash should always be
made, even if the currently executing image is compiled with
CONFIG_PM_DEVICE=n, because a previously executing image could have set
the device into DPD mode, and a call to exit_dpd is required for proper
functionality. Call `exit_dpd` regardless of the setting of
CONFIG_PM_DEVICE during QSPI nor initialization.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
Previously channels could be tore down before a sequence completes,
either when using async, or when ADC_ACTION_REPEAT was specified
The teardown is now moved to after an entire context is complete
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
This optional function allows a driver to do operations
after a complete sampling sequence is completed.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Add dependency on SYS_CLOCK_EXISTS to all timer configurations.
This would avoid a situation where a possible timer configuration would
be wrongfully selected but SYS_CLOCK_EXISTS is disabled.
This simplifies code that wants to check for system clock capabilities
don't have to check if the system clock exists in addition.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Minor rework to perform the PLLI2S VCO computations in floating point as
per the original seemingly intent.
Signed-off-by: Raul Pando <raul.pando@bytegrity.co.uk>
Point to the modified version of hal_stm32 which allow to use
ETH HAL V2 on stm32F7.
Update zephyr driver to allow it.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Similarly to what was done in USB or RNG drivers, configure 48MHz domain
clock using device tree.
By default a freq clock check is enabled.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Fix handling of failed NXP FlexCAN RX mailbox reads. Instead of re-enabling
the RX MB in the ISR, we need to handle a failed RX MB read (e.g. due to a
busy MB bit).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add a locking semaphore so that multiple threads
doing transfers with the same i2c will not produce
unexpected results. The lock will ensure that only one
transfer will happen at a time and it must be completed
before another thread can request a new transfer.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Program the right trim control register for mec150x.
This fixes uart debug console output issue.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
This change takes advantage of line information coming from new properties
to simplify exti_irq_table definition and isr routing related code.
All __stm32_exti_isr_x routing functions are removed and instead,
stm32_exti_isr is now taking a exti_range structure which provides,
for each irq, start line and range length.
This argument is provided by IRQ_CONNECT macro instead of previous
dev info (which is constant and doesn't need to be provided as argument).
line_range_x variables are generated at driver init thanks to a
mix of dt magic and runtime implementation:
DT_FOREACH_PROP_ELEM iterates over each irq line (counted as
interrupt-names property) call a macro which instantiates populated
line_range_x variables, and calls IRQ_CONNECT for each IRQ.
Additionally, at each iteration stm32_fill_irq_table() is called to
fill exti_irq_table.
Since not required anymore, Kconfig symbols EXTI_STM32_EXTIX_Y_IRQ_PRI
are removed. IRQ prio is now supposed to be configured in device tree.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The hda driver uses -EPIPE to signal xrun, as proposed in the alsa lib
https://www.alsa-project.org/alsa-doc/alsa-lib/pcm.html. This commit
changes the xrun error code in dw dma driver from -ENODATA to -EPIPE to
make it consistent across drivers.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The uart_mux_recv() documentation was wrong, the function parameters
were incorrectly documented.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
There are various call to z_soc_cached_ptr() which returns values
in the cached address space and are stored in temporary variables
that are not marked as in the cached address space. This results
in sparse complaining about discarding the cached address space
attribute. These temporary variables are then passed to other
internal memory management related functions which do not have
the concept of cached address space (as it is currently Xtensa
specific). Because of this, we cannot change the signature of
these functions. Instead, we force a change of address space
when those temporary variables are being assigned to suppress
sparse warnings.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
