Commit Graph

9 Commits

Author SHA1 Message Date
HaiLong Yang
b009cc2e18 drivers: pinctrl: add gd32f350 gpio opspeed check
Add compile time check for gd32f350 gpio opspeed.

Signed-off-by: HaiLong Yang <cameledyang@pm.me>
2021-12-13 20:27:30 -05:00
Erwan Gouriou
6026d3c5bf drivers/pinmux|pinctrl: stm32f1: Fix broken cast in remap
remap information is coded in 10 bits, uint16_t should be used
to cast it.

Fixes #40688

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 10:25:41 -05:00
Gerard Marull-Paretas
6399ad50f4 drivers: pinctrl: nrf: add support for uart/uarte peripheral
Add support for configuring UART/UARTE peripheral pins.

Co-authored-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 14:20:51 +01:00
Gerard Marull-Paretas
22c8c02145 drivers: pinctrl: nrf: initial support
Add initial support for nRF pin controller driver. The implementation in
this patch does not yet support any peripheral. Only states
representation and basic driver functionality is introduced.

Note:
The nrf_pin_configure function has been marked as __unused since it may
not be used in certain scenarios until all peripherals are supported by
the pinctrl driver. For example, if only UART/E is supported but the
board does not enable UART, the function will never get called. However,
that board will likely have other peripherals that will gain support in
the future.

Thanks to Marti Bolivar for bindings documentation.

Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 14:20:51 +01:00
Gerard Marull-Paretas
9c10e1e988 drivers: pinctrl: stm32: initial version
Add initial version for STM32 pinctrl driver. Driver has been written
re-using many of the already existing parts in
drivers/pinmux/pinmux_stm32.c.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 11:36:42 +01:00
Gerard Marull-Paretas
f8017dc5ad drivers: pinctrl: gd32: initial support for AFIO based SoCs
Add a pin control driver for GD32 SoCs using the AFIO model.

Thanks to Gerson Fernando Budke for testing and implementation
suggestions.

Co-authored-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
543a3843ff drivers: pinctrl: gd32: initial support for AF based SoCs
Add a pin control driver for GD32 SoCs using the AF model.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
329f2453c5 drivers: pinctrl: add support for dynamic pin control
Add support for dynamic pin control, that is, allow to change device pin
configuration at runtime. Because no device de-initialization is
available yet, this API has limited usage options, e.g. modify pin
configuration at early boot stage (before device driver is initialized)

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-10-25 15:26:47 -05:00
Gerard Marull-Paretas
4040df096f drivers: pinctrl: initial skeleton
Initial skeleton for pinctrl drivers. This patch includes common
infrastructure and API definitions for pinctrl drivers.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-10-25 15:26:47 -05:00