Commit Graph

7 Commits

Author SHA1 Message Date
Anas Nashif
da5f185e06 samples: add test identifier
Add unique identifier instead of just 'test' for samples.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-03-29 17:44:11 -04:00
Krzysztof Chruscinski
fdc1ee59d8 sample: subsys: logging: Ensure that logger RTT backend is tested
Logger RTT backend should be compiled on the boards that have RTT.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2019-03-28 08:41:28 -05:00
Anas Nashif
5cf49956e7 logging: add backend for xtensa simulator
Add backend for the xtensa simulator.

Fixes #10164

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-03-04 10:35:07 -05:00
Andy Ross
b69d0da82d arch/x86_64: New architecture added
This patch adds a x86_64 architecture and qemu_x86_64 board to Zephyr.
Only the basic architecture support needed to run 64 bit code is
added; no drivers are added, though a low-level console exists and is
wired to printk().

The support is built on top of a "X86 underkernel" layer, which can be
built in isolation as a unit test on a Linux host.

Limitations:

+ Right now the SDK lacks an x86_64 toolchain.  The build will fall
  back to a host toolchain if it finds no cross compiler defined,
  which is tested to work on gcc 8.2.1 right now.

+ No x87/SSE/AVX usage is allowed.  This is a stronger limitation than
  other architectures where the instructions work from one thread even
  if the context switch code doesn't support it.  We are passing
  -no-sse to prevent gcc from automatically generating SSE
  instructions for non-floating-point purposes, which has the side
  effect of changing the ABI.  Future work to handle the FPU registers
  will need to be combined with an "application" ABI distinct from the
  kernel one (or just to require USERSPACE).

+ Paging is enabled (it has to be in long mode), but is a 1:1 mapping
  of all memory.  No MMU/USERSPACE support yet.

+ We are building with -mno-red-zone for stack size reasons, but this
  is a valuable optimization.  Enabling it requires automatic stack
  switching, which requires a TSS, which means it has to happen after
  MMU support.

+ The OS runs in 64 bit mode, but for compatibility reasons is
  compiled to the 32 bit "X32" ABI.  So while the full 64 bit
  registers and instruction set are available, C pointers are 32 bits
  long and Zephyr is constrained to run in the bottom 4G of memory.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-01-11 15:18:52 -05:00
Anas Nashif
4402c4b057 samples: logger: exclude qemu_xtensa [REVERTME]
The way uart console is setup for this is not compatible with the logger
and needs additional changes, excluding until we have this implemented
in a generic way.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-05 10:09:08 -04:00
Anas Nashif
771b4defad samples: logger: test sample in CI
Add test stub for this sample to verify it in CI on default platforms.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-05 10:09:08 -04:00
Krzysztof Chruściński
3a7d4ef4cb samples: subsys: logging: Add logger example
Simple example demonstrating various logger capabilities.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2018-06-29 10:16:45 +02:00