Compilers based on Clang provide a __has_builtin(x) macro which can be
used to detect in the preprocessor if a given builtin function is
supported by the compiler.
For other compilers (notably GCC), we provide an alternative definition
of HAS_BUILTIN(x) that depends on the toolchain-specific header file to
declare which builtin functions are supported based on the current
compiler version.
Signed-off-by: Jakob Olesen <jolesen@fb.com>
Update reserved function names starting with one underscore, replacing
them as follows:
'_k_' with 'z_'
'_K_' with 'Z_'
'_handler_' with 'z_handl_'
'_Cstart' with 'z_cstart'
'_Swap' with 'z_swap'
This renaming is done on both global and those static function names
in kernel/include and include/. Other static function names in kernel/
are renamed by removing the leading underscore. Other function names
not starting with any prefix listed above are renamed starting with
a 'z_' or 'Z_' prefix.
Function names starting with two or three leading underscores are not
automatcally renamed since these names will collide with the variants
with two or three leading underscores.
Various generator scripts have also been updated as well as perf,
linker and usb files. These are
drivers/serial/uart_handlers.c
include/linker/kobject-text.ld
kernel/include/syscall_handler.h
scripts/gen_kobject_list.py
scripts/gen_syscall_header.py
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
Instead of having to enable ramfunc support manually, just make it
transparently available to users, keeping the MPU region disabled if not
used to not waste a MPU region. This however wastes 24 bytes of code
area when the MPU is disabled and 48 bytes when it is enabled, and
probably a dozen of CPU cycles during boot. I believe it is something
acceptable.
Note that when XIP is used, code is already in RAM, so the __ramfunc
keyword does nothing, but does not generate an error.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Using __ramfunc to places a function in RAM instead of Flash.
Code that for example reprograms flash at runtime can't execute
from flash, in that case must placing code into RAM.
This commit create a new section named '.ramfunc' in link scripts,
all functions has __ramfunc keyword saved in thats sections and
will load from flash to sram after the system booted.
Fixes: #10253
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
This was never a long-term solution, more of a gross hack
to get test cases working until we could figure out a good
end-to-end solution for memory domains that generated
appropriate linker sections. Now that we have this with
the app shared memory feature, and have converted all tests
to remove it, delete this feature.
To date all userspace APIs have been tagged as 'experimental'
which sidesteps deprecation policies.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This patch adds a x86_64 architecture and qemu_x86_64 board to Zephyr.
Only the basic architecture support needed to run 64 bit code is
added; no drivers are added, though a low-level console exists and is
wired to printk().
The support is built on top of a "X86 underkernel" layer, which can be
built in isolation as a unit test on a Linux host.
Limitations:
+ Right now the SDK lacks an x86_64 toolchain. The build will fall
back to a host toolchain if it finds no cross compiler defined,
which is tested to work on gcc 8.2.1 right now.
+ No x87/SSE/AVX usage is allowed. This is a stronger limitation than
other architectures where the instructions work from one thread even
if the context switch code doesn't support it. We are passing
-no-sse to prevent gcc from automatically generating SSE
instructions for non-floating-point purposes, which has the side
effect of changing the ABI. Future work to handle the FPU registers
will need to be combined with an "application" ABI distinct from the
kernel one (or just to require USERSPACE).
+ Paging is enabled (it has to be in long mode), but is a 1:1 mapping
of all memory. No MMU/USERSPACE support yet.
+ We are building with -mno-red-zone for stack size reasons, but this
is a valuable optimization. Enabling it requires automatic stack
switching, which requires a TSS, which means it has to happen after
MMU support.
+ The OS runs in 64 bit mode, but for compatibility reasons is
compiled to the 32 bit "X32" ABI. So while the full 64 bit
registers and instruction set are available, C pointers are 32 bits
long and Zephyr is constrained to run in the bottom 4G of memory.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The macros likely() and unlikely() used by the compiler for
optimization are always used inside an if condition.
According to MISRA we need to have bool type and not long.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
compiler_barrier() is itself defined down in this file. Without
adding it, newer versions of GCC (7+) for ARM Cortex-M may mistakenly
coalesce multiple strb/strh/str (store byte/half-word/word)
instructions, which support unaligned access on some
sub-architectures (Cortex-M3 and higher, but not on Cortex-M0),
into strd (store double), which doesn't support unaligned access.
Fixes: #6307
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
The logic for using _Static_assert() was a little broken. We were
using it when on GCC 4.6+ AND when __STDC_VERSION__ said we were on
C99 or better. But it's not a C99 feature, it's a C11 feature. And
if GCC provides it as an extension, that's unrelated to a particular
language version. This should have been "GCC 4.6+ OR C11+".
This actually broke on the ESP-32 IDF toolchain, where (when using
-std=c99) the compiler was actually defining a C99 macro instead of
the C11 one, and choosing to use the wrong (and independently broken)
handling incorrectly. Fixes#8093.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This patch lets a C++ application use more of Zephyr by adding guards
and changeing some constructs to the C++11 equivalent.
Changes include:
- Adding guards
- Switching to static_assert
- Switching to a template for ARRAY_SIZE as g++ doesn't have the
builtin.
- Re-ordering designated initialisers to match the struct field order
as G++ only supports simple designated initialisers.
Signed-off-by: Michael Hope <mlhx@google.com>
Added guards to the toolchain/gcc.h and toolchain/common.h
Those files should never be included directly, but a guard is useful
regardless.
Fixes#5130
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
A new arch (posix) which relies on pthreads to emulate the context
switching
A new soc for it (inf_clock) which emulates a CPU running at an
infinely high clock (so when the CPU is awaken it runs till completion
in 0 time)
A new board, which provides a trivial system tick timer and
irq generation.
Origin: Original
Fixes#1891
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
To define a system call, it's now sufficient to simply tag the inline
prototype with "__syscall" or "__syscall_inline" and include a special
generated header at the end of the header file.
The system call dispatch table and enumeration of system call IDs is now
automatically generated.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
_FILE_PATH_HASH appears to be a legacy Diab-ism that doesn't
expand to anything in GCC.
As a result, when linking the combined binary, it's quite
possible that objects in separate C files would be merged
instead of truly being in their own section. This can confound
--gc-sections and result in unused objects still being in
the final binary if one of the other objects with the same
generated section name was actually used.
We instead just use __FILE__. This results in sometimes absurdly-
long section names in the intermediate .o files, but there is no
actual limit to how long section names in ELF binaries can be;
they are not stored directly in headers but instead referenced
as an offset in the .shstrtab section, which has all the section
names stored in it.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add a macro which signals to the compiler that use of the macro is
deprecated.
Example:
#define FOO __DEPRECATED_MACRO bar
Defines FOO to 'bar' but emits a warning if used in code.
Cannot filter out with -Wno-deprecated, so be careful with -Werror.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Provide a BUILD_ASSERT and BUILD_ASSERT_MSG that are based on
_Static_assert when that's available, as its output is easier to read.
Change-Id: Ifa96d5073b1341cab2a90e4dcd04752ee80c69bb
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Some stuff that was platform-specific is made common, and some repeated
code was made a macro. __in_section() is used elsewhere in the codebase
and its 2nd and 3rd arguments are not necessarily filename/counter.
GCC-specific stuff moved to the toolchain header.
Change-Id: Ibfae919b6dd8a77210801c14e9a1128b43bd63f6
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Hamming Weight or "popcount" consists in counting the number of bits set
to 1 in a particular word. This commit adds a macro to be able to use
the existing builtin for this purpose with the GCC compiler.
Change-Id: Iec64c19e897de2bc02e981071465bbe230ee9add
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The '__unused' tag can be used to inform the compiler that a variable
might be deliberately unused. It can be used instead of ARG_UNUSED().
Change-Id: I0ec4ee92dcec29b5f9cbda362d0d6b051055628a
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Use the ALIAS_OF() macro instead of using alias attribute
directly.
Change-Id: I2f904644df2212b72d8d973bc3651dcf9e7a8b0d
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Removing _ prefix from ALIAS_OF() macro in order to indicate
that it is for public use.
The macro can be used whenever the FUNC_ALIAS() cannot. The
FUNC_ALIAS() macro can give errors if the aliased function
has parameters like uint16_t etc.
Change-Id: I2f5bc51268072141bb6fb73efe034eb743db3257
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Only define the __printf_like() toolchain macro if it is not already
defined. This permits projects to override this macro if desired.
Change-Id: Ic4a7b3eb48360f8e258493d6f447d3df793f572e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
These impede debugging and we have CONFIG_OMIT_FRAME_POINTER
now which does this globally for the entire kernel.
Change-Id: I46939223e27dd298ca3ed162ff5790cb2e9ed2a2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The toolchain headers included an abstraction for defining symbol
names in assembly context in the situation where we're using a
DOS-style assembler that automatically prepends an underscore to
symbol names.
We aren't. Zephyr is an ELF platform. None of our toolchains do
this. Nothing sets the "TOOL_PREPENDS_UNDERSCORE" macro from within
the project, and it surely isn't an industry standard. Yank it out.
Now we can write assembler labels in natural syntax, and a few other
things fall out to simplify too.
(NOTE: these headers contain assembly code and will fail checkpatch.
That is an expected false positive.)
Change-Id: Ic89e74422b52fe50b3b7306a0347d7a560259581
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Supports Internal Interrupt Controller only for now; EIC
supoort tracked in ZEP-258.
Change-Id: I2d9c5180e61c06b377fce4bda8a59042b68d58f2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Basic build framework for Nios2. Everything is stubbed out,
we just want to have a build going so that we can start to
parallelize implementation tasks.
This patch is not intended to be functional, but should be
able to produce a binary for all the nanokernel-based
sanity checks.
Change-Id: I12dd8ca4a2273f7662bee46175822c9bbd99202a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These were not actually used anywhere and weren't correct (at least
not the READ variant which assumed the architecture can always deal
with unaligned access).
Change-Id: If2bee24dc729683c839bb631d411eab73498adad
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Provide a helper to perform safe unaligned writes to data.
Change-Id: I00edde580d2ef93daaf7825d333d38fc10f854ac
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Avoid build conflict when those are defined by someone else.
Change-Id: I1bdf4064ec2180fff311c2b7a34363c53f438602
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The EXTERN_C macro is to be used to ensure compatibility between C and C++;
It prevents name mangling in C++ environments.
Change-Id: I33be727150687901f7770306c8a07c16a7e46ffa
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Use defined(__clang__) otherwise it might fail in some cases.
Change-Id: Ifb2e1cd971325e2a7f87e530e5ee921a5fcee6b9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Removed old style file description and documnetation and apply
doxygen synatx.
Change-Id: I3ac9f06d4f574bf3c79c6f6044cec3a7e2f6e4c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Adds support for static IRQ handler initialization.
Currently, IRQ_CONNECT and IRQ_CONFIG macros are emulating static
behavior through dynamic initialization.
This commit updates the macros to get real static initialization.
IRQ handlers must be assigned at build time.
Change-Id: Ia07fb25a5e4dae489f84ffcedb28007ee18a3b82
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Do not depend on environment variables and use a kconfig variable
for defining the architecture.
In addition, remove the X86_32 variable, it just duplicates X86 for
not good reason, at least until start supporting MCUs with 64bit.
Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
