Use the FSL_FEATURE_MCG_FFCLK_DIV define to decide if we should
call the api to get Fixed Frequency Clock.
This fixes Issue #49924
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This adds a very basic driver to utilize the I3C IP block
on MCUX (e.g. RT685). Note that, for now, this only supports
being the active controller on the bus.
Origin: NXP MCUXpresso SDK
License: BSD 3-Clause
URL: https://github.com/zephyrproject-rtos/hal_nxp
Commit: 2302a1e94f5bc00ce59db4e249b688ad2e959f58
Purpose: Enabling the I3C controller on RT685.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
DT node "st,stm32f105-pll2-clock" already exists but was not actually used
and PLL2 was not being configured.
PLL2 is available on STM32F105/F107 and should be turned off after turning
off PLL and turned on before turning on PLL again since PLL2 can be
used as a source for PLL. Source for PLL2 is always HSE.
Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>
On some stm32 mcus, the LSE is enabled as system clock (LSESYS)
only when the LSEON and LSERDY are both set.
The bit LSESYSEN is set in the RCC BDCR register
and the driver is waiting for the LSESYSRDY to be set.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add R-Car Gen3 PWM driver.
Clock diviser is automatically adjusted according to requested period
and duty-cycle in order to obtain as much accuracy as possible.
Indeed, in order to improve PWM accurancy, the PWM clock has to fit
the requested period. So use the given period_cycle to define if the
clock as to be adapted. In such case, increase/decrease the clock
diviser to adapt the period_cycle and be sure that it fits into the
10 bits counter of the PWM controller.
Tested on H3ULCB on pwm0 and pwm4.
Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
MCO1 is also available on STM32F1 series (on top of STM32F4), allow
selection of MCO1 source with CLOCK_STM32_MCO1_SRC_* Kconfig parameters.
Available MCO1 sources are slightly different between STM32F4
(LSE, HSE, HSI, PLLCLK) and STM32F103 (HSE, HSI, PLLCLK/2, SYSCLK), and
STM32F105/F107 have a few more (EXT_HSE, PLL2CLK, PLLI2SCLK, PLLI2SCLK/2).
MCO1 on STM32F1 does not have a configurable divider (unlike STM32F4),
HAL call only configures source.
STM32F1 do not have MCO2.
Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>
This patch adds a clock control driver for GD32 platforms. It is
important to note that the driver is only able to handle peripheral
clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On
some similar platforms (STM32) this task is embedded in the same clock
driver, performed at init time but with no options to do any
manipulation at runtime via the API calls. The clock control API as-is
is really orthogonal to "system clocks", and it is arguably a bad idea
to embed system clock init code in a clock control driver. It can be
done at SoC level still using Devicetree as a source of hardware
description/initial configuration.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
soc.h has been removed for ARM64 SoC platforms and it is also needed by
ARM32, so remove it from related drivers.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add device specific clock initialization, which uses
reset reason cause information to proper define
peripherals clock state.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
prev_temperature was only used if USE_TEMP_SENSOR is true. Make its
definition conditional.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The temperature sensor was only needed when
CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP > 0. Implementation did
not reflect this dependency correctly, and sensor sampling code was
always compiled. Also removed CONFIG_MULTITHREADING checks, since this
driver is only compiled if CONFIG_MULTITHREADING=y.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
ASSERT was failing when `r8a7795_cpg_mssr_start_stop` was
called for a "core" clock.
This ASSERT statement and "mstpcr" table of registers are
only meant to be used when starting or stopping a "module" clock.
Moved ASSERT statement to `rcar_cpg_mstp_clock_endisable`
as well as "reg" & "bit" calculation.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
STM32h7 pllout frequency calculation overflows. In the
worst case pllsrc_freq can be 50Mhz and plln_mul 512 which will cause
an overflow of the intermediate result which leads to wrong frequency
returned. As no intermediate result can be bigger than 960MHz only the
order of operations is changed.
Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>
The regulator voltage should be set before the clocks are enabled.
This is especially the case when the MSIS at 48MHz is selected as
SYSCLK.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the "zephyr/" prefix to various #include statements that are
preventing the CI form running with LEGACY_INCLUDE_PATH=n.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
MSIS frequency at boot time can be different from the one we intent to
set from device tree configuration.
In order to avoid issues, read MSIS configuration from registers to get
the actual freq rather than the devicetree one which may be not yet
configured (which is the case at startup).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
When configuring PLL, we should first make sure we're not running on PLL,
and if running on PLL, first switch to a fixed clock before proceeding
with PLL configuration.
Current code is doing the switch systematically which is not useful as
default startup case is to use MSI as sysclk source.
So add a test before doing this switch.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Unlike stated in 57df225b396e43358aac4cc998ed2e99fdb57780, RM0456.pdf
reference manual mentions about PLL1R that "Only division by 1 and even
division factors are allowed."
Though, in reference manual, there is one issue on PLL1R values
description, which should actually be:
0000000: pll1_r_ck = vco1_ck
0000001: pll1_r_ck = vco1_ck / 2 (default after reset)
0000010: Not allowed
0000011: pll1_r_ck = vco1_ck / 4
...
This description will be fixed.
Reflect this in binding and driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This power down bit of eSPI module is loacted in the bit 7 of PWDWN_CTL6
register rather than the bit 4. This commit fixs the incorrect setting.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
AST10x0 series SOCs provide the clock controller through the syscon
hardware block. The current driver supports the clock gating capability
for the hardware IPs embedded in the SOC. Each clock source has a
clock ID that can simply map to a bit in syscon registers CLK_STOP_CTRL0
(group 0) or CLK_STOP_CTRL1 (group 1). There are some clock sources
that don't have associated clock gating control, which are always on,
are grouped to into group 2.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Some Series were calculating the pll output frequency from an
clock source index instead of the clock source frequency.
This commit resolves this issue for l0, l1.
get_pllout_frequency() is only used for PLLCLK, therefore remove it.
F2, F4, and F7 have several pll dividers and might decide to implement
these as clock sources won't need PLLCLK.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Update clock_control drivers to use DT_HAS_<compat>_ENABLED Kconfig
symbol to expose the driver and enable it by default based on
devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Kumar Gala <galak@kernel.org>
The KW40Z/KW41Z don't have a Fixed Freq MCG clock so the code
associated with that in get_rate fails to build. ifdef around
the code with enum kCLOCK_McgFixedFreqClk so things work
correctly.
Signed-off-by: Kumar Gala <galak@kernel.org>
The ESP32 clock control for ESP32C3 was unified into a single
driver a while back. However the files associated with the
ESP32C3 didn't get removed than. Remove them now.
Signed-off-by: Kumar Gala <galak@kernel.org>
This commit adds required code to setup pll2 and pll3 as defined
in dts. Also these plls can now be used as alternate clock sources.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit changes the range for stm32u5 pll divider values
to allow divider value of 1.
- DIVQ is allowed to beconfigured 1 for all PLL instances
- DIVR can be 1 for PLL2 and PLL3, but is not valid for PLl1.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths
Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
irq_lock() returns an unsigned integer key.
Generated by spatch using semantic patch
scripts/coccinelle/irq_lock.cocci
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add simple clock control node in devicetree for beetle to handle
relationship between drivers (uart, timers, gpio) and clock controller
device.
Signed-off-by: Kumar Gala <galak@kernel.org>
Some stm32 devices, like stm32F4, do not have
a PLL Enable bit on the PLLP nor PLLQ divider
in their PLL config register (PLLCFGR).
The result is a empty function.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The function get_pllsrc_frequency is added
with possible source HSI or HSE.
With STM32_PLL_P_ENABLED or STM32_PLL_Q_ENABLED,
this function is used by the clock control driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
After replacing STM32_SRC_PLLCLK by the STM32_SRC_PLL_x sources
this function is no longer needed and are therefore removed.
Also, those functions returned a wrong frequency.
They should have used get_pllsrc_frequency() instead of get_pll_source()
to get the input frequency.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The SOC specific implementations of the clock_stm32_ll_common driver
included the PLL specific functions only when PLL was selected as sysclock.
This commit changes the condition from "STM32_SYSCLK_SRC_PLL"
to "defined(STM32_PLL_ENABLED)".
As a result the pll could also be used as peripheral clock source
in case it is not the sysclock.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
