This commit adds the pinctrl driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
NXP PORT IP instantiations often have different features absent, IE
input buffer, open drain, or slew rate support. Check if the relevant
PCR register bitmasks are defined in the common pin control file, and
define the bitmasks to 0x0 (no effect) if they are not. This allows us
to further consolidate the pinctrl_soc.h headers for SOCs using the PORT
IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The NXP PORT pinmuxing peripheral is reused across the MCX, S32, and
Kinetis lines. Rename the compatible from the family-specific
nxp,kinetis-pinctrl to a more generic nxp,port-pinctrl to reflect the
actual name for the IP block used within reference manuals.
Update the NXP HAL revision to include a change to use the new Kconfig
name for the PORT pinctrl driver
Update the MAINTAINERS.yml path, as there are no longer any NXP drivers
matching the string "drivers/*/*kinetis*
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove the renesas,ra-pinctrl driver, which is no longer
needed after migrating to the FSP-based implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Request and release global power domain only once during setup
of pins. Request and release involves communication over IPC and
it should be avoided if possible. For example if there are 4 pins
(like in UART) where GPD is requested we can limit number of
request/release operations fourfold.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
This patch introduces a new flag to indicate if a peripheral belongs
to FAST_ACTIVE1 domain. This way, pinctrl knows when to request the
SLOW_ACTIVE domain (where CTRLSEL multiplexer resides).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit fixes configuring pin drive strength in pinctrl driver.
Previously, there was a mismatch while filling pincfg and checking
pincfg drive strength field. This fix simplifies the operation and
avoids gpio driver header dependency.
Signed-off-by: Mert Ekren <mert.ekren@analog.com>
Co-Authored-By: Sadik Ozer <sadik.ozer@analog.com>
Add a pinctrl driver for Microchip MEC5 HAL based chips.
The driver removes the YAML enum "no change" property
value from the driver strength and slew rate properties.
Update the shared header file in mec soc common folder to
use a different Z_PINCTRL_STATE_PINCFG_INIT for MEC5.
Modifications to legacy MEC172x XEC PINCTRL will be in
a future PR.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Added a new driver to support SPI communication via EUSART. Since the
Silabs EFR32MG24 family SoCs have only one USART, EUSART support is
necessary for implementing SPI functionality.
Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
On some i.MX SoCs, such as i.MX95, the System Manager is running on a
Cortex-M core to manage the hardware resources and provide services for
SCMI requests.
So add the SCMI-based pinctrl driver to support these i.MX SoCs.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Move some STM32 drivers related Kconfig symbols from `config`
to `menuconfig` when driver options depends on these symbols.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Select PINCTRL subsystem by drivers which require it.
Prevent the need from enabling this symbol at board or soc level.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Update pinctrl driver which used for Renesas RA series with
PFS secure register
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
When setting these pins as I2C alternate mode and then setting
GCR7 or func3-ext of GPIO extended, it will cause leakage.
In order to prevent leakage, it must be set to GPIO INPUT mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Instead of forcing users to provide this setting, allow to describe
which signals require CLOCKPIN enablement at device nodes. This is later
captured by the pinctrl macros and applied in the pinctrl driver. Note
that name has been adjusted to nordic,clockpin-enable to avoid confusion
with clock related settings.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This change adds the device tree property for specifying oe-override
(output-enable override behavior), as well as defines for possible values
of the property.
RP2040 GPIOs can be configured to automatically invert the output-enable
signal from the selected peripheral function. This is useful for tasks like
writing efficient PIO code, such as in the i2c example in the rp2040
datasheet.
Signed-off-by: Yiding Jia <yiding.jia@gmail.com>
Convert pin control, GPIO and external interrupt controller drivers
based on SIUL2 peripheral to native drivers. This must be done in a
single commit to preserve atomicity, as these drivers depend on each
other.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
According to the nrfx peripheral resource sharing example in
samples/boards/nrf/nrfx_prs it should be possible to share a resource
and apply the pins on peripheral that share resource ID.
However the sample only works since it only demonstrates UART and SPIM,
and by enabling both another SPIM driver, and UART is enabled for the
console. It would not be possible to enable a TWIM driver in addition.
Instead allow the PSELs if the configuration for NRFX has been enabled.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Implementation erroneously used a mask from the ROUTEPEN register
when writing the ROUTELOC register.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Series 2 uses DBUS for alternate function control, which directly uses
port and pin numbers for location selection. Configure pinout as part
of the I2C_SDA/I2C_SCL case, rather than the separate _LOC case,
as the port and pin are not available at this point.
Configure route register prior to enabling the route, to ensure that
the wrong pin is not temporarily claimed.
Fixes an issue where DBUS was always configured to port A and
pin given by the GECKO_LOC() macro, rather than the correct port/pin
pair.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Changes to bring support for esp32c6 SoC.
- clock control
- gpio
- pinctrl
- serial
- timer
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Introduce the stm32h7RS serie to the pin control driver,
New GPIO port M, N, O, P
Then add the complete list and from A to P (16 port
coded on 5 bits)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the property of drive-strength to drive a high or low current
selection. If this property is not configured, it is the default
setting. According to the SPEC, the default drive current selection
varies from different pins.
Define the high level 0b: 8mA
low level 1b: 4mA or 2mA
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The pinctrl driver actually uses SYSCON, so 'depends on' should be used
instead of 'select'. SYSCON should be selected in SoC config instead,
just like other SoC do.
This breaks Kconfig dependency loop for configs that indirectly depends
on SYSCON and causes PINCTRL to be selected.
Signed-off-by: Patryk Duda <patrykd@google.com>
This update integrates I2C support with the pinctrl_configure_pins api
within the pinctrl_gecko driver.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@capgemini.com>
... so that the pin is kept in a defined state when the IO3 line is
not controlled by the QSPI peripheral (when the peripheral is disabled
or disconnected from the pin).
The IO3 pin in Quad SPI flash chips usually has dual functionality -
it is an I/O line when the chip is configured to work in Quad (4 I/O)
mode and it is a HOLD# or RESET# line when the chip is configured to
work in non-Quad (2 I/O) mode. In the latter case, it is important that
the line is kept in the inactive (high) state, otherwise communication
with the chip may be disrupted (and this actually happens when e.g.
the spi_flash sample is used on a brand new nRF5340 or nRF52840 DK -
the nrf_qspi_nor driver fails to initialize and the sample just ends
up with the "mx25r6435f@0: device not ready" message).
This commit addresses the problem in the same way that it was done for
the CSN line in commit 6d8172f4e9.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit enables pinctrl on i.MX8ULP. This includes:
1) Adding `pinctrl_soc.h` header file.
2) Adding DTS node for IOMUXC1, which is one of the
IPs responsible for managing the 8ULP pads.
3) Adding .dtsi with pin definitions. For now, only
the LPUART7 pads are added to this file because this
is going to be the only consummer for now.
4) Modifying the `pinctrl_imx.c` driver to work for 8ULP.
5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a
dependency of `CONFIG_PINCTRL_IMX`.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Currently, when using the `pinctrl_imx.c` driver one has
to manually enable `CONFIG_PINCTRL_IMX` even if the pinctrl
node using the driver is enabled. This is redundant and prone
to error as one would expect the driver to be enabled when
the node is also enabled.
This commit fixes the issue by enabling `CONFIG_PINCTRL_IMX`
by default and adding a new dependency on the state of the
pinctrl node (i.e: node needs to be enabled for the configuration
to also be set to `y`).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
"RW pinctrl" is clearly SOC specific naming for an IP
that is not necessarily constrained to live on one SOC series.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
