Due to the possibility of simultaneous accesess to LRCCONF registers,
additional management is required.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
This commit adds the clock driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
The `Kconfig.defconfig` is not good place for put `select PINCTRL`.
Drop `select PINCTL` from `Kconfig.defconfig` and add it at each
driver's Kconfig.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The NXP PORT pinmuxing peripheral is reused across the MCX, S32, and
Kinetis lines. Rename the compatible from the family-specific
nxp,kinetis-pinctrl to a more generic nxp,port-pinctrl to reflect the
actual name for the IP block used within reference manuals.
Update the NXP HAL revision to include a change to use the new Kconfig
name for the PORT pinctrl driver
Update the MAINTAINERS.yml path, as there are no longer any NXP drivers
matching the string "drivers/*/*kinetis*
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove the renesas,ra-clock-generation-circuit driver, which is no longer
needed after migrating to the FSP-based implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Disable every PLL before configuration. That allows
an application to reconfigure PLLs after a bootloader
configuration.
Don't disable the PLL clock if it is used by (Q|O)SPI
when executing from external memory. That will lead
to a stall.
Note: when (Q|O)SPI runs from PLL, the bootloader
dictates the clock configuration. There is no clock
reconfiguration support for memory map mode in
(Q|O)SPI drivers.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Add npcm clock control driver.
Signed-off-by: James Chiang <cpchiang1@nuvoton.com>
Signed-off-by: Joseph Liu <kwliu@nuvoton.com>
Signed-off-by: Alan Yang <tyang1@nuvoton.com>
The new update of clock device tree make the pll p q r clock
source cannot be choose by other node
This fix add 1 new dts binding for pll out p q r out line
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Instead of fixing csi2rx clock frequencies, set them according to the
pixel rate got from the camera sensor.
Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Enabled the MRT at the board level for
mcxn947. Enabled the clocking for the MRT
in the clock control.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
To check if DVFS can be used, the CONFIG_NRFS_DVFS_LOCAL_DOMAIN symbol
needs to be used, not CONFIG_NRFS_HAS_DVFS_SERVICE which only indicates
that DVFS is technically possible, not that its local domain part is
actually included in the build.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit 7a2ce2882a.
Do not enable clock control by default on nRF54H Series SoCs when
the system timer is present, because clock control is not needed
for this purpose there.
Add missing `default y` in the CLOCK_CONTROL_NRF2 Kconfig option that
enables compilation of clock control drivers for nRF54H Series.
This way modules that actually require clock control (like drivers
that use radio) will be able to enable it using the generic option
(CLOCK_CONTROL), not the above one that is specific for nRF54H.
Update accordingly applications that referenced the CLOCK_CONTROL_NRF2
option.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The Drivers using Pinctrl should be turning Pinctrl on
this should not be the responsibility of the board. This
commit removes CONFIG_PINCTRL from the boards side for nxp boards.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
STM32C0 have a different prescaler for SYSCLK and for HCLK.
Updates the clock driver to use the appropriate prescaler for each series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fixes garbage characters on mcuboot by adjusting UART baudrate
during boot phase according to clock source.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Adding the macros `RA_CGC_CLK_SRC` and `RA_CGC_CLK_DIV` that derive
the BSP clock settings from the DeviceTree node settings.
I also define some aliases to fill in the gaps with the BSP
naming conventions.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This will calibrate the HSI's PLLX clocks if enabled
The value rcc_hsicalibartion_default is 0x40U for h7/h7rs.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Deprecate support for configuring the MCO source and prescaler from
Kconfig configurations.
This is now done by devicetree and an MCO driver instead, which also
configures the pin to be used by the MCO peripheral.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add device driver for STM32 MCO peripheral which takes configures
the MCO clock source and prescaler, and outputs it on one of the GPIO
pins.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add clock sources PLL2CLK, PLL3CLK and EXT_HSE.
Needed to check that these clocks are enabled in MCO code.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
remove check for system clock frequency in clock_stm32_ll_h7 because of
addition of fracn (difficult to handle)
Signed-off-by: Nathan Olff <nathan@kickmaker.net>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Remove all entries that as not being used.
This also update hal to re-enable warning flags
as such as -Wno-unused-variable.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.
Replace z_arm_platform_init() with platform_reset().
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rather setting the driver default in soc, make it directly at symbol
level rather than soc and clean up redundant `select` occurrences.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Add custom clock_control API for nRF platforms that allows requesting
clocks with specified minimal required attributes (accuracy, precision,
and frequency). Provide an implementation of this API for FLL16M, HFXO,
HSFLL, and LFCLK controllers in the nRF54H20 SoC.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
When omitting the clk_src definition in a child node of a pclkblock,
it uses the source of the parent node.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
