- Trace32 runner: no need to configure TE bit in CFG_CORE
register in the cmm start-up script, it can be configured
at Zephyr start-up code when required (via SCTRL register)
- MPU static regions also needs to be updated for XIP and
non-XIP
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add devicetree node for code RAM, code RAM can be accessed
over AIXM bus or AXIF bus. Code access via AXIF interface
provides the best optimal performance
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This commit adds a runner wrapper for the 'minichlink' program which
offers a free, open mechanism to use the CH-LinkE programming dongle for
the CH32V003.
https://github.com/cnlohr/ch32v003fun/tree/master/minichlink
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This commit adds support for the CH32V003EVT board which features a
32-bit general-purpose RISC-V MCU.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
The ram0x partitions seem to be not compliant with nRF54H20
architecture and it causes that in the application dts overlay file
it is difficult to extend cpuapp_ram0x_region without modifying
whole layout.
It is better to place cpurad_ram0x_region at the beginning at
2f010000 address and then cpuapp_ram0x_region right after that.
Thanks to that, if the application needs to have more than 256 kB
of RAM, in the application dts overlay file, a user can increase
cpuapp_ram0x_region size up to 2f0be000.
Signed-off-by: Arkadiusz Balys <arkadiusz.balys@nordicsemi.no>
Add missing "pinctrl-names" and "status" properties for
the spi1 node in ek_ra8m1.dts to able to test spi_loopback
on ek_ra8m1
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
The B_L4S5I_IOT01A Discovery kit does not boot up when using --sysbuild.
The error is caused by slot0_partition which is assigned an address of
0x1000 which overlaps with the boot_partition. Setting the address to
0x10000 fixed it.
Signed-off-by: Winston Arrocena <we.arrocena@gmail.com>
Added mikrobus_header, mikrobus_i2c, mikrobus_spi and mikrobus_serial
node labels to da14695_dk_usb device tree board definition, allowing
compatible shield boards to be used. Also fixed minor issues with
pin assignment and header labelling.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Enable BLE feature for Nucleo-WB09KE and Nucleo-WB05KZ.
Dedicate 32KB and 8KB at the end of flash memory to storage partition on
Nucleo-WB09KE and Nucleo-WB05KZ respectively.
Add ble tag to the both devices yaml file.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
`_current` is now functionally equals to `arch_curr_thread()`, remove
its usage in-tree and deprecate it instead of removing it outright,
as it has been with us since forever.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Use a string for the mipi-mode property over an integer value, as this
significantly improves the readability of the MIPI DBI device binding.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The NXP LCDIC peripheral contains two internal timers, with configurable
periods. These times are used to determine delays within the peripheral,
such as the reset and tearing enable signal delays. Allow these periods
to be set within the devicetree for the peripheral.
Raise the period where required for display drivers that need a value
other than the reset setting
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add note about compatible change for NXP PORT IP. Also, update
references to the DT compatible within board docs.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
* Replace copies of fixed-partitions nodes in related boards by
referencing the apropriate partition table from the available list.
* For better reference the `partitions_*.dtsi` file has boot offset,
purpose and the flash size encoded in the file name. Default flash size
is considered to be 4MB.
* Added the flash size node for the boards which are not based on the
module.
* Removed flash size registry from the esp32.*common.dtsi
Signed-off-by: Marek Matej <marek.matej@espressif.com>
STM32F4 series flash layout is as follows:
{.pages_count = 4, .pages_size = KB(16)},
{.pages_count = 1, .pages_size = KB(64)},
{.pages_count = 7, .pages_size = KB(128)}
Since NVS subsys requires 2 sectors of max 32K in total, provide a
flash partition which respects this constraint using 2 of the 16K sectors
in the beginning of the layout.
Provide a compatible flash partition usable with mcuboot, but keep the
storage partition commented as its usage is not compatible with use w/o
mcuboot enabled (in this case main image starts as offset 0 which conflicts
with storage partition).
Note that it isn't possible either to get main image starting directly
in the 128K sectors w/o bootloader as boot flash address can't be
configured.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
NVS susbsystem requires a slot covering 2 sectors of flash, which
should be at minimum 8K on L1 series which provides 4K sectors.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
NVS susbsystem requires a slot covering 2 sectors of flash, which
should be at minimum 4K on G0 series which provised 2K sectors.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
STM32F2 series flash layout is as follows:
{.pages_count = 4, .pages_size = KB(16)},
{.pages_count = 1, .pages_size = KB(64)},
{.pages_count = 7, .pages_size = KB(128)}
Since NVS subsys requires 2 sectors of max 32K in total, provide a
flash partition which respects this constraint using 2 of the 16K sectors
in the beginning of the layout.
Provide a compatible flash partition usable with mcuboot, but keep the
storage partition commented as its usage is not compatible with use w/o
mcuboot enabled (in this case main image starts as offset 0 which conflicts
with storage partition).
Note that it isn't possible either to get main image starting directly
in the 128K sectors w/o bootloader as boot flash address can't be
configured.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Align the total SRAM size for STM32L47x/L48x/L49x/L4Ax
boards. Those MCUs with up to 320 Kbytes SRAM:
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Align the total SRAM size for STM32L47x/L48x/L49x/L4Ax
boards. Those MCUs with up to 320 Kbytes SRAM:
• 96 Kbytes SRAM1 and 32 Kbyte SRAM2 on STM32L47x/L48x.
• 256 Kbyte SRAM1 and 64 Kbyte SRAM2 on STM32L49x/L4Ax
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The board shares many features with other Arduinos based on STM32H747
(like the HSE in bypass mode).
Once https://github.com/zephyrproject-rtos/zephyr/pull/76542 is merged,
PF1550 support should be added too to allow switching IO voltage
from 3v3 to 1v8
Signed-off-by: Martino Facchin <m.facchin@arduino.cc>
Right now, USART1 is enabled on the M7 target variant by default, leaving
M4 without a UART to use; this is the way this port was originally
contributed.
Since then, USB was enabled on M7, changing the console backend from USART1
to USB CDC ACM; the M4 target was left unchanged.
This commit enabled USART1 on the M4 variant and disabled it on the M7
variant, so that the M4 variant can use it as its console backend.
Note that, for the M4 variant, USART1 has been assigned to `zephyr,console`
and `zephyr,shell-uart` since this port was contributed, even though USART1
was always disabled on M4.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Include in the list of supported peripherals the UARTE for the
simulated nrf54l15
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The HW models now support this peripheral for this target.
Let's enable it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The nRF54L05 and nRF54L10 are identical to the nRF54L15 except for their
memory sizes. Add support for emulating those ICs on the nRF54L15DK.
This commit only adds support for the main application core. Support for
the FLPR core may be added later.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Use the rather logical convention for the name that is applied to other
Nordic boards: <board>_common.dtsi for definitions that are common to
the board itself (LEDs, buttons, etc).
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
device tree:
enable support for the SDHC controller to use the micro SD card slot
documentation:
- added instructions for SD card and OLED samples
- added links to code samples
defconfig:
added CONFIG_ESP32_USE_UNSUPPORTED_REVISION=y to
ttgo_lora32_esp32_procpu_defconfig
The chip on the board is a ESP32 chip revision 1.
The board will not boot, it displays the following warning at boot:
I (35) boot: chip revision: v1.0
E (38) boot: You are using ESP32 chip revision (1) that is unsupported.
While it may work, it could cause unexpected behavior or issues.
E (50) boot: Proceeding with this ESP32 chip revision is not recommended
unless you fully understand the potential risk and limitations.
E (62) boot: If you choose to continue, please enable the
'CONFIG_ESP32_USE_UNSUPPORTED_REVISION' in your project configuration.
E (73) boot: HW init failed, aborting
In order to prevent a boot loop, CONFIG_ESP32_USE_UNSUPPORTED_REVISION=y
was added to the defconfig.
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Use configdefault when enabling LV_COLOR_SWAP_16 within boards and
shield definitions, to avoid OR'ing the dependencies for the Kconfig
symbol. Otherwise, a user manually selecting LV_COLOR_DEPTH will
encounter build errors as LV_COLOR_SWAP_16 may be enabled when
LV_COLOR_DEPTH_16 is not selected
Fixes#81546
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
USE_HYPERRAM macro defined shouldn't be placed under
CONFIG_BOOT_FLEXSPI_NOR.
Add flexspi1 pinmux pinctrl and flash partitions
Add flash partitions and correct flash parameter.
This commit was tested with samples: flash_shell on cm33/cm7 cores
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
A valid device tree configuration is provided for the ADCs of the 8 input
channels and the sample adc_dt works out of the box. Obviously this is
not the only possible configuration but it provides a good template for
further customization without the need to lookup the ADC GPIOs and
connections in the schematics.
Signed-off-by: Federico Di Gregorio <fog@dndg.it>
This set of changes enables the RS485 hardware connected to usart3 and
provides some overlays that allow for easily running the modbus
rtu_client and rtu_server samples on Opta.
Signed-off-by: Federico Di Gregorio <fog@dndg.it>
Some changes to cleanup and clarify some device tree nodes:
* removed wrong sdram2 definition
* added all internal flash slots accessible from M4
* added all internal flash slots accessible from M7
* removed CONFIG_UART_LINE_CTRL because not needed by USB CDC ACM
Signed-off-by: Federico Di Gregorio <fog@dndg.it>
This set of changes reorganize the ethernet configuration by removing the
use a regulator to enable the PHY: the correct GPIO pin is set in code
only if the network has been configured via CONFIG_NET_L2_ETHERNET.
Signed-off-by: Federico Di Gregorio <fog@dndg.it>
