In order to bring consistency in-tree, migrate all tests to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Both NPCX7/9 uses the IRQs at the end of the vector table, for example,
the IRQ 60 and 61 used for Multi-Input Wake-Up Unit (MIWU) devices by
default, and conflicts with ISR used for testing.
This CL changes TEST_NUM_IRQS (The value is changed from 46 to 44) to
move IRQ used for this test suite from 42 to 40 which is reserved in
both NPCX7 and NPCX9 series to resolve the issue.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
IRQ 57 is reserved in the NXP LPC55S16 SoC. Thus, limit the number of
interrupts reported to the test, so that it does not try to use it.
Fixes#34915
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
After the introduction of usart1 the kernel/genisr_table test could
no longer build, due to an interrupt conflict.
Adopt the TEST_NUM_IRQS to resolve the conflict.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The interrupt_util.h provides utils of trigger irq, now move them into
testsuite. All of the needed test cases can make use of them.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
gen_isr_table uses 6 IRQs for testing. Originally, it uses IRQ 41-36.
However, the IRQ37 & 36 are enabled by other modules in NPCX chips.
Change TEST_NUM_IRQS to use 45-40 for the test.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Modify the gen_isr_table test case to using ztest. Although it was
split up to three test cases, the test logic and the tested platform
are totally the same as previous one.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
The __attribute__((optimize("-O0"))) attribute is used to disable
optimization of some test functions. ARC MWDT toolchain doesn't
support it, however it supports __attribute__((optnone)) with
similar functionality.
Define __no_optimization attribute across all toolchains so it
can be used in tests.
NOTE: we don't define __no_optimization for XCC as it includes
GCC header with __no_optimization defined.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
In NPCX7M6FB, it uses some the IRQs at the end of the vector table,
for example, the irq 60 and 61 used for Multi-Input Wake-Up Unit (MIWU)
device by default, and conflicts with isr used for testing. Moving IRQs
for this test suite to solve the issue.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Extend the gen_isr_table test suite to build and run
on Cortex-M baseline platforms. Add a few platforms
in the whitelist so the test builds and runs for some
common Baseline Cortex-M insluding the QEMU.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In nRF9160 and application core in nRF5340, not all interrupts with
highest numbers are implemented. Thus, limit the number of interrupts
reported to the test, so that it does not try to use some unavailable
ones.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
arc emsdp's console will use irq 108/107 which will
conflict with irqs used in tests (emsdp has 112 irqs),
so add a workaround for emsdp.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Before introducing the code for ARM64 (AArch64) we need to relocate the
current ARM code to a new AArch32 sub-directory. For now we can assume
that no code is shared between ARM and ARM64.
There are no functional changes. The code is moved to the new location
and the file paths are fixed to reflect this change.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Promote the private z_arch_* namespace, which specifies
the interface between the core kernel and the
architecture code, to a new top-level namespace named
arch_*.
This allows our documentation generation to create
online documentation for this set of interfaces,
and this set of interfaces is worth treating in a
more formal way anyway.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The current implementation of kernel interrupt tests incorrectly
infers NVIC, which is specific to Cortex-M, from CONFIG_ARM.
This commit fixes such incorrect NVIC inferences by using
CONFIG_CPU_CORTEX_M instead of CONFIG_ARM.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.
Redirects for the web documentation are also included.
Then zephyrbot complained about this:
"
New files added that are not covered in CODEOWNERS:
dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi
Please add one or more entries in the CODEOWNERS file to cover
those files
"
So I assigned them to those who created them. Feel free to readjust
as necessary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Update reserved function names starting with one underscore, replacing
them as follows:
'_k_' with 'z_'
'_K_' with 'Z_'
'_handler_' with 'z_handl_'
'_Cstart' with 'z_cstart'
'_Swap' with 'z_swap'
This renaming is done on both global and those static function names
in kernel/include and include/. Other static function names in kernel/
are renamed by removing the leading underscore. Other function names
not starting with any prefix listed above are renamed starting with
a 'z_' or 'Z_' prefix.
Function names starting with two or three leading underscores are not
automatcally renamed since these names will collide with the variants
with two or three leading underscores.
Various generator scripts have also been updated as well as perf,
linker and usb files. These are
drivers/serial/uart_handlers.c
include/linker/kobject-text.ld
kernel/include/syscall_handler.h
scripts/gen_kobject_list.py
scripts/gen_syscall_header.py
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
This board is unmaintained and unsupported. It is not known to work and
has lots of conditional code across the tree that makes code
unmaintainable.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The gen_isr_table test now tries to install two dynamic
IRQ handlers.
RISCV32 has a workaround due to limited number of SW
triggerable interrupts that can be configured.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Fixes the gen_isr_table kernel test on mimxrt1050_evk by using data and
instruction synchronization barriers instead of disabling compiler
optimization on arm platforms. According to [1] section 4.5, "if a
pended interrupt request needs to be recognized immediately after being
enabled in the NVIC, add a DSB instruction and then an ISB instruction"
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHJDAAE.html
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
* add nested interrupt support for interrupts
+ use a varibale exc_nest_count to trace nest interrupt and exception
+ regular interrupts can be nested by regular interrupts and fast
interrupts
+ fast interrupt's priority is the highest, cannot be nested
* remove the firq stack and exception stack
+ remove the coressponding kconfig option
+ all interrupts (normal and fast) and exceptions will be handled
in the same stack (_interrupt stack)
+ the pros are, smaller memory footprint (no firq stack), simpler
stack management, simpler codes, etc.. The cons are, possible
10-15 instructions overhead for the case where fast irq nests
regular irq
* add the case of ARC in test/kernel/gen_isr_table
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I6c676bc6c5e850a8725785554cd535e32067f33e
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
So far, only implemented on ARM.
It's not possible to do this on Nios II and RISC-V.
Change-Id: I84c8d99cd163dff46de4bc4a7ae40768daf8e4ce
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This test is intended to verify that the SW ISR and vector tables
have been populated correctly.
Change-Id: Ic7f50c02dc0807d7ddefa710da67f818ff707ad6
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
