Commit Graph

1485 Commits

Author SHA1 Message Date
Lukasz Majewski
5a8dff59a5 stm32: Add CONFIG_DCACHE=n to stm32h7 uart API tests
As now the CONFIG_NOCACHE_MEMORY is not responsible for controlling the
data cache on STM32H7 SoC, the CONFIG_DCACHE=n must be set explicitly
to preserve previous behavior as UART driver is not using no-cache
buffers.

Considering the above comment, the CONFIG_NOCACHE_MEMORY can be safely
removed.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2022-05-24 08:47:20 -07:00
Mahesh Mahadevan
a8c7f82510 tests: counter: Fix test_multiple_alarms in counter_basic_api
Skip the test_multiple_alarms() test when the settop value is
not supported. This is to avoid the case where wrap around
take a long time thereby causing test failures

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-05-23 08:38:59 -05:00
Anas Nashif
a6f924db7f twister: add support for platform_type filter
Instead of relying on runtime filter to limit scope to emulation
platforms, use the type attribute for each platform and do the filtering
very early on. This will speed things up for tests where we only run on
emulation platforms.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-05-14 14:49:59 -04:00
Mahesh Mahadevan
95b65a4da5 tests: Add MIPI API tests
Unit tests to test the MIPI API

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-05-12 09:26:50 -05:00
Gerard Marull-Paretas
9678bd6970 pinctrl: nrf: prefix custom drive-mode property
The drive-mode property is nRF specific, so prefix it with `nordic,`,
same as the `nordic,invert` property.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-12 09:22:12 +02:00
Henrik Brix Andersen
9bd97eb0b8 drivers: can: add CAN_MODE_FD
Add support for enabling/disabling CAN-FD frame transmission/reception at
run-time.

Fixes: #45303

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-05-11 10:47:54 +02:00
Henrik Brix Andersen
6a0f3fffb5 tests: drivers: can: canfd: verify FD bit in received frames
Verify that the received frames are of the same type (CAN classic
vs. CAN-FD) as the ones sent.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-05-11 10:47:54 +02:00
Henrik Brix Andersen
3f97d11afd drivers: can: convert enum can_mode to a bit field
Convert the can_mode enum to a bit field to prepare for future extensions
(CAN-FD mode, transmitter delay compensation, one-shot mode, 3-samples
mode, ...).

Rename the existing modes:
- CAN_NORMAL_MODE   -> CAN_MODE_NORMAL
- CAN_SILENT_MODE   -> CAN_MODE_LISTENONLY
- CAN_LOOPBACK_MODE -> CAN_MODE_LOOPBACK

These mode names align with the Linux naming for CAN control modes.

The old CAN_SILENT_LOOPBACK_MODE can be set with the bitmask
(CAN_MODE_LISTENONLY | CAN_MODE_LOOPBACK).

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-05-11 10:47:54 +02:00
Henrik Brix Andersen
2f7c01ba21 drivers: can: rename API functions from timing_*_data to timing_data_*
Rename the CAN data phase API functions to timing_data_* for consistency:
- can_get_timing_min_data() -> can_get_timing_data_min()
- can_get_timing_max_data() -> can_get_timing_data_max()
- .timing_min_data -> timing_data_min
- .timing_max_data -> timing_data_max

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-05-11 10:47:54 +02:00
Henrik Brix Andersen
18890828b8 drivers: can: split CAN classic and CAN-FD syscalls
Split CAN classic and CAN-FD syscalls into two:
- can_set_timing() -> can_set_timing() + can_set_timing_data()
- can_set_bitrate() -> can_set_bitrate() + can_set_bitrate_data()

Fixes: #45303

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-05-11 10:47:54 +02:00
Erwan Gouriou
b52021189b tests/drivers/clock_control: stm32: Migrate includes to <zephyr/...>
Follow up of what was done in main branch during this development.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-10 18:42:30 +02:00
Erwan Gouriou
d9b9e12cd3 dts/bindings/clocks: stm32: 'clock-names' optional for source clock setting
Since implementation of clock source selection in consumer device drivers
could be achieved without usage of a clock-names property and no
example of usage is provided up to now, remove this property from existing
examples.
Additionally, make it clear in stm32 clock control binding that it is
driver's responsibility to correctly access clock source information
and use it as required.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-10 18:42:30 +02:00
Erwan Gouriou
ac61ea9e44 tests/drivers/clock_control: stm32: Add stm32_common_devices tests
Add a test section to enable device clock source selection testing.
Test targets I2C1 device which supports clock source selection
on all SOCs using this driver except L1
Initial test done on wb target.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-10 18:42:30 +02:00
Erwan Gouriou
17ace929f9 tests/drivers/clock_control: stm32_common: Move to stm32_common_core
Move stm32_common tests to stm32_common_core before adding new folder
for device source selection tests.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-10 18:42:30 +02:00
Erwan Gouriou
bc2a0b65a6 tests/drivers/clock_control: stm32u5: Fix pll_msis_80 test config
PLL input should be between 4 and 16MHz, so when MSI is set to 4MHz
fix PLLM can't be higher than 1.
Fix PLL1-NQR in consequence.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-10 18:42:30 +02:00
Erwan Gouriou
b821599abc tests/drivers/clock_control: stm32u5: Add a _devices test
Add a stm32u5_devices test which aims at testing devices
clock control configuration on stm32u5 targets

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-10 18:42:30 +02:00
Erwan Gouriou
c0238a7af3 tests/drivers/clock_control: stm32h7_device: Add test for CKPER source
Add 2 scenarios to test CKPER used as a clock source.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-10 18:42:30 +02:00
Erwan Gouriou
3f503e87cc boards: nucleo_h723zg: Enable SPI
Enable SPI on nucleo_h723zg board

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-10 18:42:30 +02:00
Erwan Gouriou
f61c4ae838 tests/drivers/clock_control: stm32h7_device: Use STM32_DT_CLOCKS_FOO
Make use of STM32_DT_CLOCKS_ macros to have the test work conditionally
based on alt clock presence.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-10 18:42:30 +02:00
Erwan Gouriou
78f40773b8 tests/drivers/clock_control: stm32h7: Add test for devices clock cfg
Add 2 clocks tests around device clock configuration on stm32h7.
For now, 'spi1_pllq_2_d1ppre_4' test variant is failed, which
illustrates issue reported in #41650.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-10 18:42:30 +02:00
Jordan Yates
523cd60a77 tests: build_all: modem: test esp-at
Add build tests for the `espressif,esp-at` driver, together with both
the interrupt and async variants of modem_ifact_uart.

Only build the async API variant for emulated platforms, as many
platforms do not build cleanly when `UART_ASYNC_API` is enabled without
custom setup of DMA nodes.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2022-05-10 10:44:04 +02:00
Jordan Yates
e66864e088 tests: build_all: modem: remove custom serial
Remove a custom Kconfig symbol that was used to indicate serial
interrupt support, as the test serial driver now selects the appropriate
symbols.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2022-05-10 10:44:04 +02:00
Hu Zhenyu
7d20857e4f test: Remove usec test for pwm_api
As the pwm interface only takes nanosecond for parameter,
the original test case for mircosecond is not needed.
Check github issue 44887 for more info.

Signed-off-by: Hu Zhenyu <zhenyu.hu@intel.com>
2022-05-09 11:50:40 -05:00
Gerard Marull-Paretas
d342e4c4c1 linker: update files with <zephyr/...> include prefix
Linker files were not migrated with the new <zephyr/...> prefix.  Note
that the conversion has been scripted, refer to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 12:45:29 -04:00
Erwan Gouriou
eb2e718556 tests: Migrate overlay includes to <zephyr/...>
Leftover of work done on #45420 and #45417.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-09 10:34:42 -04:00
Gerard Marull-Paretas
ade7ccb918 tests: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all tests to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 20:02:14 +02:00
Jan Peters
88ca4fb533 tests: drivers: counter: add mimxrt QTMR to counter_basic_api test
to test basic functionality of the new mcux_qtmr counter driver.

Signed-off-by: Jan Peters <peters@kt-elektronik.de>
2022-05-03 20:41:23 -05:00
Daniel DeGrasse
409cc23022 drivers: disk: remove legacy nxp USDHC driver
all in tree SOCs with the USDHC peripheral have now been converted to
use the new SD host controller USDHC driver, so remove legacy NXP disk
USDHC driver.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
5b5e01bc69 tests: sdhc: Add SD host controller driver test
SD host controller driver runs basic SD host controller tests, including
checking SD presence, and sending commands to SD card. No data transfer
is performed.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Leonard Pollak
f7171e20b3 tests: drivers: Add bme680-spi to build_all
Add BME680 (SPI) sensor driver to build_all tests.

Signed-off-by: Leonard Pollak <leonardp@tr-host.de>
2022-04-28 18:11:50 +02:00
Derek Snell
6115cf0a4d tests: drivers: i2s_speed: enable testing on mimxrt1170_evk board
Readme instructions for connecting SAI4 as TX to SAI1 as RX on this
board.  Also includes overlay and Kconfig settings to run this test
on the board.

Signed-off-by: Derek Snell <derek.snell@nxp.com>
2022-04-28 14:18:00 +02:00
Derek Snell
0356a70397 tests: drivers: i2s_speed: place mem_slab's in non-cacheable region
If platform supports non-cacheable region, place mem_slab's for I2S
driver buffers there.  This enables drivers using DMA without cache
coherency issues.

Signed-off-by: Derek Snell <derek.snell@nxp.com>
2022-04-28 14:18:00 +02:00
Gerard Marull-Paretas
ae91933c4a drivers: pwm: always use nanoseconds for set
In order to be consistent with what is possible in Devicetree, always
take a period in nanoseconds. Other scales or units may be specified by
using, e.g., the PWM_MSEC() macros (all of them converting down to
nanoseconds). This change then deletes the "_nsec" and "_usec" versions
of the pwm_set call.

Note that this change limits the period to UINT32_MAX nanoseconds,
~4.3s. PWM is, in generali, used with periods below the second so it
should not be a problem.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-04-28 11:29:38 +02:00
Gerard Marull-Paretas
10ee44c94b drivers/samples/tests: remove usage of deprecated PWM APIs
Use the new API calls that remove pin naming.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-04-28 11:29:38 +02:00
Mahesh Mahadevan
6a66493703 tests: counter: Update test_multiple_alarms test
Set the top value relative to the current time. This is
so that we avoid the case of setting the top value that
is prior to the current value.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-04-28 10:26:54 +02:00
Henrik Brix Andersen
dcf833d971 tests: drivers: spi: loopback: add olimex_esp32_evb configuration
Add configuration for testing SPI loopback on the Olimex ESP32-EVB
board.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-04-28 10:26:40 +02:00
Anas Nashif
97a55d6a25 tests: uart: fix integration platforms
Fix usage of integration_platforms and apply it individually instead of
the common section.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-04-27 12:26:22 -04:00
Hake Huang
07d6adde51 driver: adc: fix build error for adc_dma
fsl_sim.h is not required as SDK upgrade

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-04-27 11:15:43 -05:00
Jordan Yates
1d189487b4 tests: spi: spi_loopback: use gpio_dt_spec fields
Use the gpio_dt_spec fields of `struct spi_cs_control`, instead of the
deprecated individual fields.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2022-04-23 21:11:29 +02:00
Jordan Yates
d6c3b0a40a tests: spi: spi_loopback: cleanup code formatting
Cleanup split lines and invalid whitespace.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2022-04-23 21:11:29 +02:00
Daniel DeGrasse
a59b308e73 tests: uart_async_api: skip test cases if LPUART is present without DMA
if DMA support is not present, LPUART driver will not compile when async
API support is required. Skip test cases when dma support is not present
and LPUART driver is enabled.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-22 09:44:19 +02:00
Daniel DeGrasse
fee7de48d3 tests: uart_async_api: add nxp,loopback mode to boards with LPUART
add nxp,loopback mode to boards with LPUART. This will enable testing
the UART async api without a physical loopback connection.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-22 09:44:19 +02:00
Erwan Gouriou
531c484958 tests/drivers/clock_control: stm32_common: Test HCLCK instead of SYSCLK
Rework test_*_freq to test HCLK freq instead of SYSCLK one, as it is not
correct to compare CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC with SYSCLK.

Additionally, add a test to verify use of AHB prescaler.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-04-21 14:09:44 +02:00
Erwan Gouriou
d8f5ef725f tests/drivers/clock_control: stm32u5: Rework to explicitly test HCLK
Instead of testing SysClockFreq setting, we should instead check HCLK
setting which is the real zephyr CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
counterpart (core clock freq) and takes AHB prescaler setting into
account.

Additionally, update one test configuration to explicitly verify AHB
prescaler is correctly taken into account by clock driver.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-04-21 14:09:44 +02:00
Erwan Gouriou
da370ea720 tests/drivers/clock_control: stm32l0/l1: MSI range 11 is not allowed
Remove L0 and L1 targets from "sysclksrc_msi_48" test case as this
MSI range 11 is not an allowed value on these series.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-04-21 14:09:44 +02:00
Erwan Gouriou
fa85670f1b tests/drivers/clock_control: stm32f1: HSI clock is 8MHz
On STM32F series, HSI clock is 8MHz, fix test using 16MHz
and a test name.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-04-21 14:09:44 +02:00
Jordan Yates
37aa5fa90a tests: console: extend semihost_console testing
With SEMIHOST_CONSOLE now being supported on all ARM, ARM64 and RISC-V
architectures, extend the testing to cover these cases.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2022-04-21 13:04:52 +02:00
Jordan Yates
070422db46 arch: common: dedicated SEMIHOST symbol
Control the usage of semihosting with a dedicated symbol, instead of
implying semihosting from the usage of `SEMIHOST_CONSOLE`. This allows
semihosting to be used without the semihost console.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2022-04-21 13:04:52 +02:00
Henrik Brix Andersen
e777aa823b tests: drivers: can: api: verify filters persist through bitrate changes
Verify that added rx filters are preserved through bitrate changes.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-04-21 13:00:46 +02:00
Bartosz Bilas
2d3011c9b4 tests: drivers: spi: don't use deprecated spi_cs_control struct members
gpio_dev is being deprecated in favor of gpio_dt_spec gpio member
so let's use it instead of that one.

Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
2022-04-21 13:00:35 +02:00