Commit Graph

7 Commits

Author SHA1 Message Date
Anas Nashif
470c5f3189 tests: remove testcase.ini files
We now use yaml files.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-21 20:56:53 -04:00
Anas Nashif
cc24f4b03c tests: samples: convert testcase files to yaml
This will prepare test cases and samples with metadata and information
that will be consumed by the sanitycheck script which will be changed to
parse YAML files instead of ini.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-21 20:56:53 -04:00
Kumar Gala
eaaa175b92 tests: convert to using newly introduced integer sized types
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.

Jira: ZEP-2051

Change-Id: I6c676bc6c5e850a8725785554cd535e32067f33e
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 09:53:49 -05:00
Jean-Paul Etienne
9acda0f695 tests: gen_isr_table: account for riscv32 architecture
Account for riscv32 SOCs supporting the riscv privileged architecture.

Change-Id: I8c26a2bcc2baded5db252896abe6e1b5ab052113
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-02-22 14:59:01 +00:00
Anas Nashif
b62fbccce1 tests: gen_isr_table: disable for cortex-m0
Change-Id: Ic4c3ee2d319e60af166786b856384ee421526b81
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-02-15 00:05:14 -08:00
Andrew Boie
5c335ce55f tests: gen_isr_table: actually run the IRQ
So far, only implemented on ARM.
It's not possible to do this on Nios II and RISC-V.

Change-Id: I84c8d99cd163dff46de4bc4a7ae40768daf8e4ce
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-15 04:49:18 +00:00
Andrew Boie
122467e9ee tests: add test for gen_isr_table
This test is intended to verify that the SW ISR and vector tables
have been populated correctly.

Change-Id: Ic7f50c02dc0807d7ddefa710da67f818ff707ad6
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 01:28:00 +00:00