This change adds support for segger rtt, similar to other supported
soc's. This was lacking when evaluating tracing.
Without this addition the system fails to build, indicating that
HAS_SEGGER_RTT is missing. Adding CONFIG_HAS_SEGGER_RTT in prj.conf is
not allowed.
Signed-off-by: Bart De Vos <bart.devos@verhaert.com>
Add CONFIG_SECOND_CORE_MCUX_LAUNCHER. This Kconfig is only enabled when
using sysbuild targeting the Cortex-M4 core on the RT11xx series, and
results in loading a minimal application to the Cortex-M7 core that
boots the Cortex-M4 core. This makes developing on the M4 core simpler,
as the user can now simply target the core with sysbuild enabled and
flashing the application will work as expected.
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Although I/DCACHE aren't included under cm33 architecture,
NXP design and integrate Code Cache/Sys Cache for cm33 to
speed up the core execution efficiency.
For the convenience of developers, we believe that software
developers can directly use Code/Sys Cache as arm's I/D Cache.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Enable CONFIG_GIC_SAFE_CONFIG by default for Cortex-A Core platforms
as the most targets are to run multiple OSes together with Zephyr on
different Cortex-A Cores.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add the DWARF v5 sections to the linker scripts of
imx, imxrt, acp_6_0 and xtensa_sample_controller.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Now that MbedTLS is capable of automatically enabling
CONFIG_ENTROPY_GENERATOR (when available), we can remove forced
enablements in boards|soc deconfig files.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
This is based on the introduction of a helper Kconfig symbol in
"subsys/random/Kconfig" which is named CSPRNG_AVAILABLE. When this is
enabled it means that there is a "zephyr,entropy" property defined in the
device-tree, therefore Mbed TLS can select ENTROPY_GENERATOR to allow
the platform specific driver to be included into the build.
This commit also changes other locations where CSPRNG_ENABLED was used
moving it to CSPRNG_AVAILABLE in order to solve dependency loop
build failures.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Creation of the new zephyr\soc\nxp\common\nxp_nbu.c driver which manage
the interruption of the NBU. This modification is mandatory to support a
coex application which includes Bluetooth and 802.15.4 on the same
narrow band path.
Signed-off-by: Xavier Razavet <xavier.razavet@nxp.com>
Enable CONFIG_HAS_MCUX_IGPIO because device driver CONFIG_GPIO_MCUX_IGPIO
depends on it, so that the driver can be enabled by dts nodes.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
LinkServer can flash only the first time, cannot flash again.
Fix it by setting default mcu security status as unsecure.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Rename "nxp,kinetis-lpuart" compatible to "nxp,lpuart" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Combine BLE and 802.15.4 monolithic build under a single config to make
it less error prone.
The choice between a BLE/802.15.4 combo firmware and a BLE only firmware
is done depending on the Soc (like RW610 vs RW612).
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
- Adds a flash runner configuration for mcxn/c/a/w
used for sysbuild multi-image projects.
- Solves sysbuild issue with multiple resets and mass erases.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
On NXP RT1170 SOC, ADC ETC exists but it can not be enabled because
of dependency on HAS_MCUX_ADC_ETC.
Also, ADC ETC should only work with ADC together, there is no use
case to run it standalone.
Fixes:#81466
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
In the IOMUXC controller, the PDRV field uses 0b0 to set the pin drive
to high, and 0b1 to set the pin to normal drive. Fix the pinctrl_soc.h
definitions for the iMXRT11xx parts to use the correct setting for this
register, based on the documentation for the pin control binding
Note that for PDRV type pins, this commit effectively switches their
drive strength setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Following the binding rename to "nxp,sysmpu", update the Kconfig
option to align with the binding name and to better reflect the
option's purpose.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Many NXP socs had the following defconfig:
```
config PINCTRL_IMX
default y if HAS_IMX_IOMUXC
depends on PINCTRL
```
However, the PINCTRL_IMX option already has:
```
config PINCTRL_IMX
bool "Pin controller driver for iMX MCUs"
depends on DT_HAS_NXP_IMX_IOMUXC_ENABLED
depends on HAS_MCUX_IOMUXC || HAS_IMX_IOMUXC
default y
help
Enable pin controller driver for NXP iMX series MCUs
```
So the soc level defconfigs are redundant.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
- Disables on reset NMI and EzPort.
- Fixes possible reset and power-on issues.
- Already applied for K64, now applying for the rest of Kinetis.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
- Trace32 runner: no need to configure TE bit in CFG_CORE
register in the cmm start-up script, it can be configured
at Zephyr start-up code when required (via SCTRL register)
- MPU static regions also needs to be updated for XIP and
non-XIP
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Use Zephyr cache API to initialize cache as done for
various platforms. Enabling CACHE_MANAGEMENT by default
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
NXP PORT IP instantiations often have different features absent, IE
input buffer, open drain, or slew rate support. Check if the relevant
PCR register bitmasks are defined in the common pin control file, and
define the bitmasks to 0x0 (no effect) if they are not. This allows us
to further consolidate the pinctrl_soc.h headers for SOCs using the PORT
IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
add flexspi.c file to get flexspi clock rate.
Enable flexspi1 clock if don't boot from flash.
Use custom fixed mpu_regions.c file to config MPU for CM7
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
What is changed?
Use CMSIS SystemCoreClock via a dedicated flag instead of using
soc flags.
Why do we need this change?
This change is part of cleaning soc specific code out of arch folder.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The FRDM_MCXW71 Platform has a reserved IRQ as its
last IRQ, this test was using this IRQ to
test an interrupt and would not fire. This change
ensures the test does not use the reserved IRQ.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
When option ARM_MPU is disabled exclude soc\nxp\imxrt\mpu_regions.c.
It is needed to remove constraints of SRAM and FLASH size.
Fixes#70920
Signed-off-by: Grixa Yrev <GrixaYrev@yandex.ru>
As for the IMX SOCs all the lines removed in this commit were
actually commented out so there's basically no change in code
behavior expected here.
The only affected SOCs family is therefore the Kinetis one.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
RT11xx SOC init should check to see if the zephyr flash node is
set to a device on the FLEXSPI bus to determine if the part is running
in XIP mode. This check was incorrect, so the FLEXSPI was being
reclocked in XIP mode to 24 MHz. Fix this check so the FlexSPI is not
downclocked.
Fixes#75702
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Do not select HAS_SEGGER_RTT unless the segger module is present. This
avoids a Kconfig error when SEGGER's debug module is not present in the
west manifest
Fixes#80529
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
There is a typo in the part number list for LPC55S69. The
LPC55S69JET98 should be LPC55S69JEV98.
Fixes#80541
Signed-off-by: David Leach <david.leach@nxp.com>
Instead of fixing csi2rx clock frequencies, set them according to the
pixel rate got from the camera sensor.
Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
