After updating the "st,stm32-vref" binding with a new property containing
the calibration data resolution ("vrefint-cal-resolution"), update the
corresponding nodes in SoC DTSI files with the proper value.
Note that the property is not set on SoCs with resolution of 12, as it is
the default value specified for the property in the binding.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add support for STM32H757 SoC, which shares its design
with STM32H747 with added cryptography peripherals.
Signed-off-by: Grzegorz Runc <g.runc@grinn-global.com>
- provide support for the STM32C071 serie
- add stm32g0-flash-controller compatible on flash node
to fix CI issue on undefined reference to
`flash_stm32_page_layout'
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
The STM32F4 socs have different channels for the temperature sensor.
Some are at channel 16 and some at channel 18. Made changes wherever it
was relevant.
In short, the base configuration is to channel 16 and wherever it is
supposed to be 18 it is overridden.
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
This commit Introduces DTS configurations for DMA,
SPI, RNG, Crypto, USB and RTC modules to enable
support in STM32U0.
Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
In all STM32 dtsi and board dts, update the st,adc-sequencer and the
st,adc-clock-source properties so they are strings.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
fu dts: arm: st: use string instead of enum
Add a clk48Mhz node to the stm32f412 serie.
This clock is sourced by PLL_Q (default) or PLLI2S_Q
That 48MHz clock is used by the USB /SDMMC/RNG peripherals.
The sdmmc/SDIO clock is sourced by this CK48 (default)
or by the SYSCLOCK.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds the main DTS configurations required
to enable I3C support on STM32.
Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
Introduce new binding "st,stm32u5-otghs-phy" for OTG_HS PHY. This allows to
configure clock source and handle STM32U5 specific OTG_HS PHY behavior in
driver implementation in a more readable way.
Move OTG_HS PHY clock selection (previously <&rcc STM32_SRC_HSI48
ICKLK_SEL(0)>) from OTG_HS node to OTG_HS PHY node.
Rename USBPHYC_SEL -> OTGHS_SEL which matches the definition in the stm32u5
CCIPR2 register (RM0456 Rev 5, Section 11.8.47).
Support enabling OTG_HS PHY clock, which is bit 15 (OTGHSPHYEN) in
RCC_AHB2ENR1. Change OTG_HS clock to be bit 14 (OTGEN).
Calculate in runtime OTG_HS PHY clock source frequency. Try to match that
to supported (16, 19.2, 20, 24, 26, 32 MHz) frequencies and select proper
option with HAL_SYSCFG_SetOTGPHYReferenceClockSelection() API (instead of
hardcoded 16 MHz selection).
Co-authored-by: Adrian Chadd <adrian.chadd@meta.com>
Signed-off-by: Adrian Chadd <adrian.chadd@meta.com>
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
The compatible: "st,stm32h7-hsi-clock" has HSI clock divider
required which is set to 1, by default, delevering 64MHz
in the stm32h7.dtsi and stm32h7rs.dtsi
(As done for stm32h5 and other series)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Split and fix the total SRAM size for STM32L4Px/L4Qx/L4Rx/L4Sx
device. Those MCUs with up to 640 Kbytes SRAM:
This is 640KB for the STM32L4Rxxx and STM32L4Sxxx devices :
• 192 Kbytes SRAM1 + 64 Kbytes SRAM2 + 384 Kbytes SRAM3
This is 320KB for the STM32L4P5xx and STM32L4Q5xx devices :
• 128 Kbytes SRAM1 + 64 Kbytes SRAM2 + 128 Kbytes SRAM3
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Split and fix the total SRAM size for STM32L47x/L48x/L49x/L4Ax
device. Those MCUs with up to 320 Kbytes SRAM:
• 96 Kbytes SRAM1 and 32 Kbyte SRAM2 on STM32L47x/L48x.
• 256 Kbyte SRAM1 and 64 Kbyte SRAM2 on STM32L49x/L4Ax
The sram0 node at address 0x20000000 and sram1 at address 0x10000000
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This moves the SRAM definitions for STM32H56/7x chips up to the top
level since they are common to all of them.
Signed-off-by: Djordje Nedic <nedic.djordje2@gmail.com>
- stm32cO11/31 share the same spi peripheral
- include stm32_dma header to be able to configure
spi with dma config macros (STM32_DMA_PERIPH_TX,...)
in dts
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Define the "clocks" property, for the flash "st,stm32h7-flash-controller"
node, only for the stm32H7 dual-core devices
which have the RCC bit 8 present in their RCC AHB3 register.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
PR #79683 missed a few nodes introduced while it was under review.
Replace the remaining raw values with STM32_CLOCK in WB0 DTSI files.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add stm32h7 ethernet compatible "st,stm32h7-ethernet",
used also for stm32h5.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Add I2C and SPI Device Tree nodes in SoC DTSI files to allow usage of these
peripherals.
Note that the SPI driver requires no modification to be functional on WB0.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The stm32l4 devices were previously assigned the generic STM32 AES driver,
which turned out to be incompatible with the stm32l4 series. This commit
updates the nodes to use the new driver specifically designed for this
series.
Add missing node for stm32l4a6, stm32l4q5, stm32l4s5 and stm32l486 socs.
It appears stm32l4p5 and stm32l496 socs do not have the AES accelerator
present, so the nodes are removed from the dts files.
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
For STM32L1, U5 and WBA, the ADC always uses an asynchronous clock source,
so we add the default clock source in the clock node.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Change the STM32 Temperature Sensor bindings to accept the average slope
value in string form instead of integer. With this change, it is possible
to use the raw decimal value found in each MCU's datasheet instead of
needing to scale it (differently depending on series!). This also allows
regrouping the property in a single file to reduce duplication.
Also update all DTSI files affected by this change and the dietemp driver
to accept the property's new format.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The typical value for V25 is different on the STM32F100 line compared
to other STM32F1 MCUs. Update the DTS property to the correct value.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add the missing 'avgslope' property to the DTSI for STM32F030/STM32F070.
This fixes improper results being returned by the driver: the correct
value for the average slope is 4.3mV/°C (4300 µV/°C), but the binding's
default value of 2.53mV/°C was used instead, since property was missing.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Remove the "Negative Temperature Coefficient" attribute from the STM32F2
die temperature sensor node, as it does not correspond to the hardware.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add MCO device nodes to the STM32 boards.
The set of supported boards are chosen to replace what is currently
supported in Kconfig.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add clock sources that can be output by the MCO on the stm32f1x and
stm32f10 connectivity line devices.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Adds Device Tree include files for all MCUs in the STM32WB0 series.
These DTSI files only contain the supported peripherals for now.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
we have four i2C peripherals .
- three shared between stm32u031/73/83
- One between stm32u073/83
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
The STM32 SPI driver, `spi_ll_stm32.c`, reads the clock frequency via
`clock_control_get_rate()`. The first `clocks` index is used as subsystem
argument if there is no second index, but this is not the source clock for
SPI 1, 2, and 3.
This causes the prescaler value calculation to be incorrect, resulting in a
frequency potentially above the `spi-max-frequency` value.
Add clock source for SPI instances 1, 2 and 3, that matches the default
clock configuration register reset value, which resolves the issue.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
since stm32h7.dtsi is already include in st/h7/stm32h743.dtsi
we don't need to include here again.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
The flash controller is nowadays supported on the M4 core.
Add the bank2-flash-size property to the board definitions as required
by the STM32 H7 flash driver.
Signed-off-by: Tomi Fontanilles <tomi.fontanilles@nordicsemi.no>
