- Bring macro defined of RA8 in flash_hp_ra.h to device tree
- Change to use irq_lock instead of semaphore for code flash
- Modify and add conditions to check and make decision to perform
action at last block.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
After writing option bytes, force them to be loaded. Failing to perform
this step means the values are never applied and not actually written
to non-volatile memory.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Do not unlock CR at the end of initialization.
The lock mechanism is to protect unwanted registers modifications due to
software bugs. There is no point in leaving the registers unlock once
the driver is initialized.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
The CMD_BLANK_CHECK can return errors when the flash is readable, and
should only be used after programming, not in is_area_readable(). From
the LPC55S69 datasheet: "As cells age and lose charge, a correctly
programmed address will fail this check, while still being able to be
read successfully for the remaining duration of the data retention time."
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Use uint64_t instead of uint32_t for the FLASH_STM32_EX_OP_SECTOR_WP
extended operation.
Some chips have two banks, more than 16 sectors each e.g. stm32h7a3xx
chips, so more than 32 bits are required.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
XIP prefetching seems to still be running, even while interrupts are
disabled. Therefore it is important to wait for the FlexSPI to be idle
before performing a write/erase operation.
Signed-off-by: Martin Stumpf <martin.stumpf@vected.de>
Enable buffered write for nRF54l RRAM flash driver by default.
CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE=1 means that write will be buffered
by 16 B buffer (native RRAM write-bock-size).
This allows optimal life-endurance of RRAM memory.
For reference" DTS declares 16 write-block-size already.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Adapt the stm32 flash driver for the stm32h7rs serie where some
bit of the FLASH registers are named differently from stm32h7 serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Use shell_device_get_binding() instead of device_get_binding() so that
we get the device based on its name and in addition by its label.
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
When the CONFIG_BT_STM32WBA the stm32wba_fm flash driver is compiled
and must takes flash_stm32_sem_take/give functions from the
flash_stm32.h header file, like other stm32 series.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add two new flash extended operations for reading and writing STM32
option bytes from the application code.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Currently, MT25 flashes were running in 3-byte mode.
This is not compatible with the chip we use in our project (MT25QU01GBBB),
as only 128 Mbit of its 1 Gbit can be addressed.
Signed-off-by: Martin Stumpf <finomnis@gmail.com>
Implement the readout protection for the STM32H7 series.
Define the specific functions used by the flash_stm32h7.
Move the stm32h7 flash register manipulation in a write_optb()
to be called by the flash_stm32_set_rdp_level.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Place the flash_stm32_sem_take and flash_stm32_sem_give
function to header file for common to use in any flash driver
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The FlexSPI NOR driver should verify all 3 bytes of the JEDEC ID match
the expected value before attempting to use a custom LUT table with a
flash chip. This reduces the odds that an incompatible LUT will be used
with a flash chip, as some flash chips may share the same first byte of
their device ID but not be compatible with the custom LUT table.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
some flashes support special opcodes
for 4-byte addressing, that can be used
without switching to 4-byte mode.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The flash_flexspi_nor_check_jedec() checks the lower 16-bits of
the manufacturer ID and installs a custom LUT table.
Add an exception to check for the whole 32-bits so we do not
accidentally install custom LUT for flash devices that do not
support this LUT table.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The CONFIG_PINCTRL is removed from the board's defconfig files.
Drivers which use pin control function should add "select PINCTRL"
in their Kconfig files.
Fixes#78619
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The current alignment logic does not work as expected if given unaligned
values, resulting in a skip of the first word. The length also has to
take into account the starting address: for example, asking for 2 bytes
at offset 3 should actually check 8 bytes.
This patch adjusts the logic so that it always includes the first and
the last word of the input area.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
As other targets in the LPC55xxx series, the LPC55S36 has a Flash
controller that raises ECC errors when reading erased pages directly.
To avoid this, there is special code for this platform that calls the
HAL FLASH_IsFlashAreaReadable() function. However, this in turn calls a
function at an hardcoded address in ROM that _always_ causes an
instruction fault, making the situation worse.
This patch reworks the read operation to use the FLASH_Read() HAL
function for this target to gracefully handle error conditions and
properly emulate accesses to erased pages. The preprocessor is required
since some targets do not define the FLASH_Read() function.
Fixes: #80325
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Not all the stm32H7 have a clock enable for their flash;
only the dual-core.
For the st,stm32h7-flash-controller with "clocks" property, the driver
will enable the flash clock bit in the corresponding RCC register.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The struct jesd216_bfp was declared as __packed but later in the code
the address of a member was given to a non-packed pointer, potentially
causing reading of wrong addresses, and causing warnings with the
IAR ICCARM compiler.
After studying the JEDEC documentation JESD216F.02, section
6.4.2 JEDEC Basic Flash Parameter Header: 2nd DWORD, the struct must
be aligned to 4 so __packed is not necessary, just 4 byte alignment.
Signed-off-by: Lars-Ove Karlsson <lars-ove.karlsson@iar.com>
lots of values from the DT where not set corretly, if
`CONFIG_SPI_NOR_SFDP_RUNTIME` was
enabled. This fixes it.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
